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c(0) <= not c(0); carry(0) := c(0); c(1)<= c(1) xor carry(0); carry(1) := c(1) and carry(0); c(2)<= c(2) xor carry(1); carry(2) := c(2) and carry(1); c(3)<= c(3) xor carry(2); carry(3) := c(3) and carry(2); c(4)<= c(4) xor carry(3); carry(4) := c(4) and carry(3); c(5)<= c(5) xor carry(4); carry(5) := c(5) and carry(4); c(6)<= c(6) xor carry(5); carry(6) := c(6) and carry(5); c(7)<= c(7) xor carry(6); carry(7) := c(7) and carry(6); 
Hi there, anyone can explain the whole coding above for me? I need each explanation for each line. Thanks alot.
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Is the code snipped above in a clocked process ? Maybe you are able to post the whole code, so we can see it in connection. best regards Tobias
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity my_counter is port(count: Out std_logic_vector(7 downto 0); clk: in std_logic; reset: in std_logic); end my_counter; architecture behav_my_counter of my_counter is signal c : std_logic_vector(7 downto 0) := "00000000"; begin ctr: process(clk,reset) variable carry : std_logic_vector(7 downto 0) := "00000000"; begin if reset'event and(reset = '1') then c <= (others => '0'); elsif clk'event and (clk = '1') then i am adding "00000001" to 'c'. this is done using basic logic gates.  the equation for full adder is simplified and written below. full adder equations are:  sum = A xor B xor Carry.  carry = (A and B) or (A and carry) or (B and carry). subsititue B with "00000001" here and you will get the below equations. c(0) <= not c(0); carry(0) := c(0); c(1)<= c(1) xor carry(0); carry(1) := c(1) and carry(0); c(2)<= c(2) xor carry(1); carry(2) := c(2) and carry(1); c(3)<= c(3) xor carry(2); carry(3) := c(3) and carry(2); c(4)<= c(4) xor carry(3); carry(4) := c(4) and carry(3); c(5)<= c(5) xor carry(4); carry(5) := c(5) and carry(4); c(6)<= c(6) xor carry(5); carry(6) := c(6) and carry(5); c(7)<= c(7) xor carry(6); carry(7) := c(7) and carry(6); end if; end process; count <= c; end behav_my_counter; 
This is the full coding. You want me to post the test bench too?
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Kelly N. wrote: > Hi there, anyone can explain the whole coding above for me? > I need each explanation for each line. I don't think that makes any sense, because each line itself describes, what it does... :o Much more useful is a description, what the whole thing does... It is a synchronous counter: http://faculty.kfupm.edu.sa/COE/ashraf/RichFilesTe... http://tamswww.informatik.unihamburg.de/applets/...
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Like I still don't understand how it works. Why is the coding like this. & why we need to c(0) <= not c(0); in the first place.
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if you count up, the LSB is always alternating. this is what this particular line does. all other lines represent adders. carry(x) holds the carry of the addition 'before' the bit. c(1)<= c(1) xor carry(0); carry(1) := c(1) and carry(0); 0+0 = 00 1+0 = 01 0+1 = 01 1+1 = 10 the XOR calculates the LSB, the AND the MSB of each addition.
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Alright. This applies to all the lines after that right? But why in the first place they need c(0) <= not c(0); the initial of c(0) is 00000000 am I right?
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Kelly N. wrote: > the initial of c(0) is 00000000 am I right? Ist is only one bit and therefore just '0'... :/ > Like I still don't understand how it works. > Why is the coding like this. > & why we need to > c(0) <= not c(0); > > in the first place. Did you have a look for http://tamswww.informatik.unihamburg.de/applets/... Did you see the most left XOR? With the enable signal permanently '1' this is just an inverter. And that results in a simple NOT. If you want to describe the schematic there http://tamswww.informatik.unihamburg.de/applets/... you must do it that way (referring to your posted code):
process(clk,reset) variable carry : std_logic_vector(7 downto 0) := "00000000"; begin if reset = '0' then c <= (others => '0'); elsif clk'event and (clk = '1') then c(0) <= c(0) xor enable; carry(0) := c(0) and enable; c(1) <= c(1) xor carry(0); carry(1) := c(1) and carry(0); : 
BTW: You will not find this component on any FPGA (hardly anywhere on earth):
if reset'event and(reset = '1') then  not synthesizeable : elsif clk'event and (clk = '1') then : end if; 
It seems to me thats Verilog thinking: always @(posedge reset)... But you will not find a flipflop, thats sensitive to two (different) clock signals!!! Instead the Reset is level sensitive:
if reset = '0' then  as long as reset is '0' : elsif clk'event and clk = '1' then : end if; 
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Whats your question? What do you not understand? > But why in the first place they need > c(0) <= not c(0); If you pick any stage in the middle of the code and do a slightliy reformatting, then you see
: c(2) <= c(2) xor carry(1); carry(2) := c(2) and carry(1); c(3) <= c(3) xor carry(2); carry(3) := c(3) and carry(2); : 
Each stage refers to the previous stage. So for a 212 bit witdh the last entries will be
: c(210) <= c(210) xor carry(209); carry(210) := c(210) and carry(209); c(211) <= c(211) xor carry(210); carry(211) := c(211) and carry(210); 
Its easy, isn't it? And now: what to do with stage 0?
c(0) <= c(0) xor carry(1); carry(0) := c(0) and carry(1); c(1) <= c(1) xor carry(0); carry(1) := c(1) and carry(0); : 
And because we don't have a stage '1' we substitute it with a logic '1':
c(0) <= c(0) xor '1'; carry(0) := c(0) and '1'; c(1) <= c(1) xor carry(0); carry(1) := c(1) and carry(0); : 
And now a little bit boolean equation magic: What is XX AND '1'? Correct answer: XX What is YY XOR '1'? Correct answer: NOT YY And if you take this knowledge into your code it results in:
c(0) <= NOT c(0); carry(0) := c(0); c(1) <= c(1) xor carry(0); carry(1) := c(1) and carry(0); : 
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I think somehow I understand. But I want to ask one very stupid question. <= & := what's the different & means?
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> <= & := what's the different & means?
Take ANY VHDL book and have a look for the different behaviuor of
signals and variables.
And after that: as a VHDL beginner forget_variables for (at least) the
next half year!
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c(0) <= not c(0); carry(0) := c(0); c(1) <= c(1) xor carry(0); carry(1) := c(1) and carry(0); c(2)<= c(2) xor carry(1); carry(2) := c(2) and carry(1); 
Hi, I could get the waveform from 00000000, 00000001, 000000010, 00000011. But I don't understand how it get with the coding above. I understand the first 2 lines. But from 3rd lines onwards, I couldn't understand. When i work out, I get c(1) = '1'  00000010 carry(1) = '1'  00000010 c(2) = '1'  00000100 carry(2) = '1' 00000100 Is this the correct way of doing?
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> I understand the first 2 lines.
I'm not sure with that...
Lets say we start with values like this:
s is a std_logic signal
v is a std_logic variable
Lets define:
Both of them start with a value '0', so we have s = '0' and v = '0'
And now we add a clock and enter a process like this:
signal s : std_logic := '0'; process (clk) variable v : std_logic := '0'; begin if rising_edge(clk) then s <= '1'; v := s; end if; end process; 
So tell me: whats the value of s and v after one rising edge of clk? And now the same here:
signal s : std_logic := '0'; process (clk) variable v : std_logic := '0'; begin if rising_edge(clk) then v := '1'; s <= v; end if; end process; 
Again: telle me whats the value of s and v after one rising edge of clk?
> c(2) = '1'  00000100
This is nonsense: you cannot subtract a vector from one bit!
But I understand what you mean... ;)
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signal s : std_logic := '0';
process (clk)
variable v : std_logic := '0';
begin
if rising_edge(clk) then
s <= '1';
v := s;
end if;
end process;
So tell me: whats the value of s and v after one rising edge of clk?
s = 1
v = 1 ?
signal s : std_logic := '0';
process (clk)
variable v : std_logic := '0';
begin
if rising_edge(clk) then
v := '1';
s <= v;
end if;
end process;
Again: telle me whats the value of s and v after one rising edge of clk?
s = 1
v = 1 ?
> c(2) = '1'  00000100
This is nonsense: you cannot subtract a vector from one bit!
But I understand what you mean... ;)
I mean c(2) = 00000100 not 100000100. :D
But is it correcT?
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> Again: telle me whats ... s = 1 v = 1 ? The second one you got correct. > So tell me: whats the value .... s = 1 v = 1 ? Wrong! In the first sample we have s = '1' and v = '0'. Thats the behaviour of signals!!! (And your problem at the moment!) The value of each signal remains throughout the whole process. The assignment of the signals "new" value is done at "end process". So check this:
signal a,b,c : std_logic := '0'; process (clk) variable x,y,z : std_logic := '0'; begin if rising_edge(clk) then a <= '1'; b <= a; x := b; y := '1'; c <= y; z := c; end if; end process; 
Whats the result?
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Kelly N. wrote: > s = 1 > v = 1 ? > ... > s = 1 > v = 1 ? This is your guess. What is the result from your simulator? Duke
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> What is the result from your simulator?
One should not need a simulator for this...
But it could be a tool to come behind the (different) behaviour of
signals and variables in a process ;)
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So check this: signal a,b,c : std_logic := '0'; process (clk) variable x,y,z : std_logic := '0'; begin if rising_edge(clk) then a <= '1'; b <= a; x := b; y := '1'; c <= y; z := c; end if; end process; Whats the result? 
a = 1 b = 1 x = 0 y = 0 c = 1 z = 0 Correct?
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> Correct? Whats your simulators opinion? > Correct? No... :( This is the result: a = 1 b = 0 !! x = 0 y = 1 !! c = 1 z = 0 The short way: Variables take over the new value immediately. Signals take over the last assigned value at the end of the process.
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I'm confuse now. We should look at the operator (<= / :=) or ?
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> We should look at the operator (<= / :=) or ?
Not particular!
The assignment token is just a indication for a signal or a variable.
The := is the assignment symbol necessary for variables, the <= is the
one for the signals.
You must know the difference of the behaviour between signals and
variables, not the difference of the assignment tokens. If you ause the
:= instead of the <= then your simulator/synthesizer generates a error.
But if you use a variable where you should use a signal, then no error
is generated, but you get a different behaviour...
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I don't know the behaviour of signals and variables. Can explain a bit to me?
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> I don't know the behaviour of signals and variables. > Can explain a bit to me? I did already... :/ But here once more: a signal keeps its entry value throughout the whole process. At the end of the process it takes over the last assigned value. A variable takes immediately over the assigned value. See this:
signal s integer := 123; process (clk) variable v : integer := 987; begin if rising_edge(clk) then s <= 345;  next_s = 345, current_s = 123 s <= 876;  next_s = 876, current_s = 123 v := s;  v = current_s = 123 s <= 555;  next_s = 555, current_s = 123 v := 777;  v = 777 s <= v;  next_s = v = 777; end if; end process;  assign s = next_s 
So at the end of this process we have s = 777, v = 777 And now you must take any book about VHDL and a simulator and check it out for yourself.
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Sorry, I got question on my coding. Let's say
c(1) <= c(1) xor carry(0); carry(1) := c(1) and carry(0); 
c(1) = '0' carry(0) = '1' I need find out carry (1) c(1) <= c(1) xor carry(0); 0 xor 1 = 1 So c(1) <= next = 1, current = 0 ? am I right? Then when I need to find the carry (1) := c(1) and carry(0); the c(1) which value should I use?
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> the c(1) which value should I use? c is a signal and therefore it does not change its value until the end of the process. Then it will get the last assigned value. > c(1) = '0' > carry(0) = '1' > I need find out carry (1)
c(1) <= c(1) xor carry(0);  c(1)_current='0' > c(1)_next='1' carry(1) := c(1) and carry(0);  c(1)_current='0' > carry(1) ='0' 
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Hi, I got question. [code] C(0) <= NOT c(0); Carry(0) := c(0); C(1) <= c(1) XOR carry (0) Carry(1) := c(1) AND c(0) If I were to keep contiune process. I would need to run again and again. I got mix up. The coding start with 00 00 01 10 11 I should get this result I try to work it out but I got confuse. C(0) <= NOT c(0);  c(0) = current: 0. Next: 1 Carry(0) := c(0);  carry(0)= 0 C(1) <= c(1) XOR carry (0).  c(1) = current: 0. Next: 0 Carry(1) := c(1) AND c(0)  carry(1)= 0 Am I right? Which value should I use when I execute again? I got confuse by this.