There are no previously attached files... :-/
At least I didn't find any.
This is your "problem"
when 17 =>
if (A(7) xor B(7)) = '1' then
product <= not ACC(15 downto 0) + '1';
You assign the final value after 17 clocks. So until then the result is
A solution for you is to assign a default value to Product like this:
entity mult8X8 is
port (Clk, St: in std_logic;
Mplier,Mcand : in std_logic_vector(7 downto 0);
Product: out std_logic_vector(15 downto 0) := (others => '0'); -- some little magic here
Done: out std_logic);
BTW: do you know, that VHDL has a multiplication operator, the '*'?
So you could smply write: Product <= Mplier * Mcand;