There are no previously attached files... :-/
At least I didn't find any.
However:
This is your "problem"
1 | when 17 =>
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2 | if (A(7) xor B(7)) = '1' then
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3 | product <= not ACC(15 downto 0) + '1';
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You assign the final value after 17 clocks. So until then the result is
-U-ndefined.
A solution for you is to assign a default value to Product like this:
1 | entity mult8X8 is
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2 | port (Clk, St: in std_logic;
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3 | Mplier,Mcand : in std_logic_vector(7 downto 0);
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4 | Product: out std_logic_vector(15 downto 0) := (others => '0'); -- some little magic here
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5 | Done: out std_logic);
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6 | end mult8X8;
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BTW: do you know, that VHDL has a multiplication operator, the '*'?
So you could smply write: Product <= Mplier * Mcand;