library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; use IEEE.numeric_bit.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY mult8X8testbench IS END mult8X8testbench; ARCHITECTURE behavior OF mult8X8testbench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT mult8X8 PORT( Clk : IN std_logic; St : IN std_logic; Mplier : IN std_logic_vector(7 downto 0); Mcand : IN std_logic_vector(7 downto 0); Product : OUT std_logic_vector(15 downto 0); Done : OUT std_logic ); END COMPONENT; constant N: integer := 4; type arr is array(1 to N) of std_logic_vector(7 downto 0); constant Mcandarr: arr := ("01100110","10100110","01101011","11001100"); constant Mplierarr: arr := ("00110011","01100110","10001110","10011001"); --Inputs signal Clk : std_logic := '0'; signal St : std_logic := '0'; signal Mplier : std_logic_vector(7 downto 0) := (others => '0'); signal Mcand : std_logic_vector(7 downto 0) := (others => '0'); --Outputs signal Product : std_logic_vector(15 downto 0); signal Done : std_logic; -- Clock period definitions constant Clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: mult8X8 PORT MAP ( Clk => Clk, St => St, Mplier => Mplier, Mcand => Mcand, Product => Product, Done => Done ); Clk<= not Clk after 10ns; -- Clock process definitions Clk_process :process begin for i in 1 to N loop Mcand <= Mcandarr(i); Mplier <= Mplierarr(i); St <= '1'; wait until Clk = '1' and Clk'event; St <= '0'; wait until done = '1'; wait until Clk = '1' and Clk'event; end loop; Clk <= '0'; wait for Clk_period/2; Clk <= '1'; wait for Clk_period/2; end process; -- Stimulus process ----stim_proc: process ----begin -- hold reset state for 100 ns. ----wait for 100 ns; ----wait for Clk_period*10; -- insert stimulus here ----wait; ----end process; END;