help:Why YAGARTO can't accept the option"-mcpu=cortex-m4" ?

cortex m. OP (Company: cumtb) #2154501
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The newest YAGARTO GNU ARM toolchain is with GCC-4.6,and the GCC-4.6 
should support cortex-m4 using the option "-mcpu=cortex-m4"(refer to 
http://gcc.gnu.org/gcc-4.6/changes.html).
But when I using the option "-mcpu=cortex-m4",it show

Error: unknown cpu `cortex-m4'
Error: unrecognized option -mcpu=cortex-m4

So why it can not support the option?
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cortex m. OP (Company: cumtb) #2171458
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Michael Fischer wrote:
> Hello,
>
> perhaps the next version will support M4.
>
> Regards,
> mifi

Thanks for reply,It can support the cortex-m4 in the newest version.
But I can't use  floating point arithmetic in my C program.

=======
main.o: In function `main':
D:\cygwin\home\houxn\main\m3/main.c:6: undefined reference to
`__aeabi_fmul'
D:\cygwin\home\houxn\main\m3/main.c:6: undefined reference to
`__aeabi_fmul'
======

I think it may lack soft-float library,but I don't know how to solve it.
Moreover,I want to use FPU in cortex-m4,it can not generate FPU code
like "VMUL.F32      s3,s1,s0"
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Michael F. #2172190
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Hello,

>Thanks for reply,It can support the cortex-m4 in the newest version.
>But I can't use  floating point arithmetic in my C program.
Soft floating point is working, take a look in the K40
example here:
http://www.yagarto.de/download/yagarto/K40Test.zip

>I think it may lack soft-float library,but I don't know how to solve it.
>Moreover,I want to use FPU in cortex-m4,it can not generate FPU code
>like "VMUL.F32      s3,s1,s0"
Use the option "-mfloat-abi=hard". I think this should produce
code for a FPU unit.

Btw, which CPU you are using?

Regards,
mifi
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cortex m. OP (Company: cumtb) #2173378
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Michael Fischer wrote:
> Hello,
>
>>Thanks for reply,It can support the cortex-m4 in the newest version.
>>But I can't use  floating point arithmetic in my C program.
> Soft floating point is working, take a look in the K40
> example here:
> http://www.yagarto.de/download/yagarto/K40Test.zip
>
>>I think it may lack soft-float library,but I don't know how to solve it.
>>Moreover,I want to use FPU in cortex-m4,it can not generate FPU code
>>like "VMUL.F32      s3,s1,s0"
> Use the option "-mfloat-abi=hard". I think this should produce
> code for a FPU unit.

Thanks a lot! I just make it successfully by using the option 
"-mfloat-abi=hard".

My CPU is K60,a product of Freescale.32-bit ARM Cortex-M4 core with DSP 
support MPU.
I thought that the free GNU tools would not support so new CPU but only 
Keil etc..But I was wrong.


Another question is that if I use cortex-m3 (without DSP unit),how can I 
do if I want it generates soft-float code ?
I just use "-mfloat-abi=soft",but it was wrong:
----
undefined reference to `__aeabi_fmul'
undefined reference to `__aeabi_fmul'
----
How can I do ?

Where can I find the support information such as use "-mfloat-abi=hard" 
or what files should I refer to ?

Thanks!
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Jörg W. Moderator #2173418
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cortex m4 wrote:

> Where can I find the support information such as use "-mfloat-abi=hard"
> or what files should I refer to ?

1
$ arm-none-eabi-gcc --target-help

2
The following options are target specific:

3
  -mabi=                      Specify an ABI

4
  -mabort-on-noreturn         Generate a call to abort if a noreturn function

5
                              returns

6
  -mandroid                   Generate code for the Android operating system.

7
  -mapcs-float                Pass FP arguments in FP registers

8
  -mapcs-frame                Generate APCS conformant stack frames

9
  -mapcs-reentrant            Generate re-entrant, PIC code

10
  -march=                     Specify the name of the target architecture

11
  -mbig-endian                Assume target CPU is configured as big endian

12
  -mcallee-super-interworking Thumb: Assume non-static functions may be called

13
                              from ARM code

14
  -mcaller-super-interworking Thumb: Assume function pointers may go to non-

15
                              Thumb aware code

16
  -mcirrus-fix-invalid-insns  Cirrus: Place NOPs to avoid invalid instruction

17
                              combinations

18
  -mcpu=                      Specify the name of the target CPU

19
  -mfix-cortex-m3-ldrd        Avoid overlapping destination and address

20
                              registers on LDRD instructions that may trigger

21
                              Cortex-M3 errata.

22
  -mfloat-abi=                Specify if floating point hardware should be used

23
  -mfp16-format=              Specify the __fp16 floating-point format

24
  -mfpu=                      Specify the name of the target floating point

25
                              hardware/format

26
  -mhard-float                Alias for -mfloat-abi=hard

27
  -mlittle-endian             Assume target CPU is configured as little endian

28
  -mlong-calls                Generate call insns as indirect calls, if

29
                              necessary

30
  -mpic-register=             Specify the register to be used for PIC addressing

31
  -mpoke-function-name        Store function names in object code

32
  -msched-prolog              Permit scheduling of a function's prologue

33
                              sequence

34
  -msingle-pic-base           Do not load the PIC register in function prologues

35
  -msoft-float                Alias for -mfloat-abi=soft

36
  -mstructure-size-boundary=  Specify the minimum bit alignment of structures

37
  -mthumb                     Compile for the Thumb not the ARM

38
  -mthumb-interwork           Support calls between Thumb and ARM instruction

39
                              sets

40
  -mtp=                       Specify how to access the thread pointer

41
  -mtpcs-frame                Thumb: Generate (non-leaf) stack frames even if

42
                              not needed

43
  -mtpcs-leaf-frame           Thumb: Generate (leaf) stack frames even if not

44
                              needed

45
  -mtune=                     Tune code for the given processor

46
  -mvectorize-with-neon-quad  Use Neon quad-word (rather than double-word)

47
                              registers for vectorization

48
  -mword-relocations          Only generate absolute relocations on word sized

49
                              values.

50
  -mwords-little-endian       Assume big endian bytes, little endian words

51


52
  Known ARM CPUs (for use with the -mcpu= and -mtune= options):

53
    cortex-m0, cortex-m1, cortex-m3, cortex-r4f, cortex-r4, cortex-a9,

54
    cortex-a8, cortex-a5, arm1156t2f-s, arm1156t2-s, mpcore, mpcorenovfp,

55
    arm1176jzf-s, arm1176jz-s, arm1136jf-s, arm1136j-s, arm1026ej-s, arm926ej-s,

56
    iwmmxt2, iwmmxt, xscale, arm1022e, arm1020e, arm10e, arm968e-s, arm966e-s,

57
    arm946e-s, arm9e, arm1020t, arm10tdmi, ep9312, arm940t, arm922t, arm920t,

58
    arm920, arm9tdmi, arm9, arm740t, arm720t, arm710t, arm7tdmi-s, arm7tdmi,

59
    strongarm1110, strongarm1100, strongarm110, strongarm, arm810, arm8,

60
    arm7dmi, arm7dm, arm7m, arm7500fe, arm7500, arm7100, arm710c, arm720,

61
    arm710, arm700i, arm700, arm70, arm7di, arm7d, arm7, arm620, arm610, arm600,

62
    arm60, arm6, arm3, arm250, arm2

63


64
  Known ARM architectures (for use with the -march= option):

65
    iwmmxt2, iwmmxt, ep9312, armv7e-m, armv7-m, armv7-r, armv7-a, armv7,

66
    armv6-m, armv6t2, armv6zk, armv6z, armv6k, armv6j, armv6, armv5te, armv5e,

67
    armv5t, armv5, armv4t, armv4, armv3m, armv3, armv2a, armv2

68
 ARM-specific assembler options:

69
  -k                      generate PIC code

70
  -mthumb                 assemble Thumb code

71
  -mthumb-interwork       support ARM/Thumb interworking

72
  -mapcs-32               code uses 32-bit program counter

73
  -mapcs-26               code uses 26-bit program counter

74
  -mapcs-float            floating point args are in fp regs

75
  -mapcs-reentrant        re-entrant code

76
  -matpcs                 code is ATPCS conformant

77
  -mbig-endian            assemble for big-endian

78
  -mlittle-endian         assemble for little-endian

79
  -mapcs-frame            use frame pointer

80
  -mapcs-stack-check      use stack size checking

81
  -mno-warn-deprecated    do not warn on use of deprecated feature

82
  -mcpu=<cpu name>        assemble for CPU <cpu name>

83
  -march=<arch name>      assemble for architecture <arch name>

84
  -mfpu=<fpu name>        assemble for FPU architecture <fpu name>

85
  -mfloat-abi=<abi>       assemble for floating point ABI <abi>

86
  -meabi=<ver>            assemble for eabi version <ver>

87
  -mimplicit-it=<mode>    controls implicit insertion of IT instructions

88
  -EB                     assemble code for a big-endian cpu

89
  -EL                     assemble code for a little-endian cpu

90
  --fix-v4bx              Allow BX in ARMv4 code

91


92
Linker options

93
==============

94


95
Use "-Wl,OPTION" to pass "OPTION" to the linker.

96


97
armelf: 

98
  --build-id[=STYLE]          Generate build ID note

99
  -Bgroup                     Selects group name lookup rules for DSO

100
  --disable-new-dtags         Disable new dynamic tags

101
  --enable-new-dtags          Enable new dynamic tags

102
  --eh-frame-hdr              Create .eh_frame_hdr section

103
  --hash-style=STYLE          Set hash style to sysv, gnu or both

104
  -z combreloc                Merge dynamic relocs into one section and sort

105
  -z defs                     Report unresolved symbols in object files.

106
  -z execstack                Mark executable as requiring executable stack

107
  -z initfirst                Mark DSO to be initialized first at runtime

108
  -z interpose                Mark object to interpose all DSOs but executable

109
  -z lazy                     Mark object lazy runtime binding (default)

110
  -z loadfltr                 Mark object requiring immediate process

111
  -z muldefs                  Allow multiple definitions

112
  -z nocombreloc              Don't merge dynamic relocs into one section

113
  -z nocopyreloc              Don't create copy relocs

114
  -z nodefaultlib             Mark object not to use default search paths

115
  -z nodelete                 Mark DSO non-deletable at runtime

116
  -z nodlopen                 Mark DSO not available to dlopen

117
  -z nodump                   Mark DSO not available to dldump

118
  -z noexecstack              Mark executable as not requiring executable stack

119
  -z now                      Mark object non-lazy runtime binding

120
  -z origin                   Mark object requiring immediate $ORIGIN

121
                                processing at runtime

122
  -z max-page-size=SIZE       Set maximum page size to SIZE

123
  -z common-page-size=SIZE    Set common page size to SIZE

124
  -z KEYWORD                  Ignored for Solaris compatibility

125
  --thumb-entry=<sym>         Set the entry point to be Thumb symbol <sym>

126
  --be8                       Output BE8 format image

127
  --target1=rel               Interpret R_ARM_TARGET1 as R_ARM_REL32

128
  --target1=abs               Interpret R_ARM_TARGET1 as R_ARM_ABS32

129
  --target2=<type>            Specify definition of R_ARM_TARGET2

130
  --fix-v4bx                  Rewrite BX rn as MOV pc, rn for ARMv4

131
  --fix-v4bx-interworking     Rewrite BX rn branch to ARMv4 interworking veneer

132
  --use-blx                   Enable use of BLX instructions

133
  --vfp11-denorm-fix          Specify how to fix VFP11 denorm erratum

134
  --no-enum-size-warning      Don't warn about objects with incompatible

135
                                enum sizes

136
  --no-wchar-size-warning     Don't warn about objects with incompatible

137
                                wchar_t sizes

138
  --pic-veneer                Always generate PIC interworking veneers

139
   --stub-group-size=N   Maximum size of a group of input sections that can be

140
                           handled by one stub section.  A negative value

141
                           locates all stubs after their branches (with a

142
                           group size of -N), while a positive value allows

143
                           two groups of input sections, one before, and one

144
                           after each stub section.  Values of +/-1 indicate

145
                           the linker should choose suitable defaults.

146
  --[no-]fix-cortex-a8        Disable/enable Cortex-A8 Thumb-2 branch erratum fix
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Michael F. #2173917
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>Another question is that if I use cortex-m3 (without DSP unit),how can I
>do if I want it generates soft-float code ?
>I just use "-mfloat-abi=soft",but it was wrong:
>----
>undefined reference to `__aeabi_fmul'
>undefined reference to `__aeabi_fmul'
>----
>How can I do ?
Take a look here at my examples page:
http://www.yagarto.de/examples/index.html

Take one example, DO NOT change the makefile, and
add a multiplication. It will work, have make a
fast test with the LPC1343.
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cortex m. OP (Company: cumtb) #2174126
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Michael Fischer wrote:

> Take a look here at my examples page:
> http://www.yagarto.de/examples/index.html
>
> Take one example, DO NOT change the makefile, and
> add a multiplication. It will work, have make a
> fast test with the LPC1343.


Thanks,I have solved my problem.
When linking,I used "arm-none-eabi-ld" but the example above use 
"arm-none-eabi-gcc",and the latter is work.

I have built my own toolchain in fedora refer to your 
build-scripts-20110429.
Before that I have built "arm-elf-*" toolchain,but it have some 
problems(and I can't explain why).

Now the "arm-none-eabi-*" toolchain works well,and I find it appears 
more efficient than windows version.But the windows version is more 
convenience,because I have to run VMware if I want to use linux version.
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Ilija K. #2194215
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cortex m4 wrote:
> Michael Fischer wrote:
>> Hello,
>>
>>>Thanks for reply,It can support the cortex-m4 in the newest version.
>>>But I can't use  floating point arithmetic in my C program.
>> Soft floating point is working, take a look in the K40
>> example here:
>> http://www.yagarto.de/download/yagarto/K40Test.zip
>>
>>>I think it may lack soft-float library,but I don't know how to solve it.
>>>Moreover,I want to use FPU in cortex-m4,it can not generate FPU code
>>>like "VMUL.F32      s3,s1,s0"
>> Use the option "-mfloat-abi=hard". I think this should produce
>> code for a FPU unit.
>
> Thanks a lot! I just make it successfully by using the option
> "-mfloat-abi=hard".
>
> My CPU is K60,a product of Freescale.32-bit ARM Cortex-M4 core with DSP
> support MPU.

Hi

Has your K60 an FPU? I have got TWR-K60N512-KIT but it has no FPU.

Ilija
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Ilija K. #2194479
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Hi Michael

Michael Fischer wrote:
> Hello Ilija,
>
> I have only a K40 but if you compare the both picture from:
>
> K40:
> http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=K40
>
> K60:
> http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=K60
>
> It looks that the K60 had a floating point unit.

FPU is an option for K60, but I don't know if there are ones with FPU 
available yet. Mine is without.

I have built (just-enough) GCC 4.6.0 only to discover that FPU is 
missing.

Regards
Ilija
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Ilija K. #2194712
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Michael Fischer wrote:
> Hello Ilija,
>
> what is the full product number of your device?
> Compared to the "Product Brief" of the K60 you will
> find the information in section "4.3 Part Numbers and
> Packaging". Here specially the "Key attribute".
>
> Do you have a K60D or K60F?

D and F are new markings introduced a week ago. Old markings (check 
older Product brief release if you have on) do not contain D/F 
designation.

FYI present TWR modules have chip with designation K60N512VMD100

Ilija
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