Hi Harald,

Thanks for the reply.

My intention is to force SUM signal to (A & B & CIN) between 15 and 35 
units.

I am a beginner at Verilog, and I am new to force/release statements. So 
I wanted to test these statements out in Verilog.

I suspect the output SUM is being forced to 0 instead of (A & B & CIN) 
between 15 and 35. As you can see at time 25 units in the simulation 
output, A = 1, B = 1, CIN = 1... but SUM = 0.

Perhaps I am making a fundamental mistake, but SUM(at #25)
= A & B & CIN = 1 & 1 & 1 = 1

I tested the #35 release SUM instead of #35 release FA.sum. The port 
collapsing does make SUM and FA.sum the same signal.

Edwards

Hi Harald,

I tested out the program as you mentioned and it does assign SUM to a 
static value calculated at time #15.

That explains what is going on. Thanks for your help :)

Edwards

John Edwards wrote:
> That explains what is going on.

I am afraid it doesn't. The force/release in this context is a 
"procedural continuous assignment" (IEEE 1364-2005, sec. 9.3) which 
means: "[...]if any variable on the right-hand side of the assignment 
changes, the assignment shall be reevaluated while the assign or force 
is in effect."

A major commercial simulator returns this:

1

#     Time  CIN  A  B  COUT  SUM

2

#        0    0  0  0     0    0

3

#        5    0  0  1     0    1

4

#       10    0  1  0     0    1

5

#       15    0  1  1     1    0

6

#       20    1  0  0     0    0

7

#       25    1  1  1     1    1

8

#       30    1  1  0     1    0

9

#       35    1  1  1     1    1

Kind regards
Marcus
http://www.doulos.com/

Hmm...

Thanks for pointing that out.

From what I have read, force/release statements are supposed to act 
differently on nets and registers.

For nets, they should be reevaluated (like in this case for SUM, i 
think). For regs, they should be evaluated only once(at force) and the 
same value is forced.

I made a very simple AND module to test it out:

1

2

 module Top;

3

  reg a;

4

  reg b;

5

  wire A;

6

  wire B;

7

  wire c;

8

9

  //Testing force and release for wire arguments

10

  assign A = a;

11

  assign B = b;

12

  assign c = A | B; //All wires in this expression. Force 

13

                    //statement should definitely reevaluate

14

15

  initial 

16

  begin

17

    $monitor($time, "\t%b\t%b\t|%b", a, b, c);

18

  end

19

20

  initial

21

  begin

22

    a = 1'b0; b = 1'b0;

23

24

    #5 a = 1'b1; b = 1'b1;  <------ #5

25

    force c = A & B;

26

27

    #5 a = 1'b1; b = 1'b0;

28

    #5 a = 1'b1; b = 1'b1;

29

    #5 a = 1'b1; b = 1'b1;

30

    #5 a = 1'b0; b = 1'b1;

31

    #5 a = 1'b1; b = 1'b0;

32

    #5 a = 1'b1; b = 1'b1;

33

    #20 release c;

34

  end

35

 endmodule

Note: Don't get confused with c = A & B. I just wanted all arguments and 
assigned LHS to be wires.

If I execute the case above, I always get 1 as below:

1

#00     0  0  |  0

2

#05     1  1  |  1       <---- force start

3

#10     1  0  |  1

4

#15     1  1  |  1

5

#25     1  1  |  1

6

#30     0  1  |  1

7

#35     1  0  |  1

8

#55     1  1  |  1       <---- release

If I change the test case {1 1} at time #5 to {1 0}, I get all 0 until 
release:
i.e.

1

#00     0  0  |  0

2

#05     1  0  |  0

3

#15     1  1  |  0

4

#25     1  1  |  0

5

#30     0  1  |  0

6

#35     1  0  |  0

7

#55     1  1  |  1

ICARUS verilog is treating both regs and nets the same way, forcing both 
of them to a static value evaluated at #5.

Can someone confirm this reasoning?

Edwards

Hello,

There is a way to obtain the required behaviour from force/release 
statements. Referring to the code, I posted in my first post(4-bit Full 
adder), instead of writing the statements in the 'Top' module:

1

2

initial begin

3

    #15 force SUM = A & B & CIN;

4

    #20 release FA.sum;  

5

end

We should write it as:

1

2

wire expr;

3

assign expr = A & B & CIN

4

5

initial begin

6

    #15 force SUM = expr;

7

    #20 release FA.sum;  

8

end

This appears to behave correctly for Icarus Verilog version 0.9.3. The 
bug report status is still open. I have borrowed this from the comments 
section of the bug report on Source Forge tracker here:

http://sourceforge.net/tracker/index.php?func=detail&aid=2459145&group_id=149850&atid=775997

entitled "Procedural continuous assign or force is only evaluated once - 
ID: 2459145".

Thanks

Edwards

Perhaps yes, as it appears to be an icarus simulator based issue.

Anyhow, it would be nice to have these posts here, just incase somebody 
else comes across this issue.

Edwards

John Edwards wrote:
> For nets, [the RHS expression of a force statement] should be
> reevaluated (like in this case for SUM, i think). For regs, they
> should be evaluated only once (at force) and the same value is
> forced.

Where did you read that? The main difference between a var and a net
in this context is the behavior when released again. A var keeps its
(forced) value while a net assumes the resolved value of all its drivers
immediately.

--
Marcus

Hi Marcus,

Correct again. I was under the wrong impression that reg would evaluate 
RHS expression only once with a value forced on it until it is released, 
but they also re-evaluate expressions assigned to them.

I was confused by the wording in my textbook:
   "The register var will continue to store the forced value after being 
released, but can then be changed by a future procedural assignment."

My apologies. Thanks for pointing that out.

Edwards