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Forum: FPGA, VHDL & Verilog errors in floating point adder


von Mostafa M. (Company: aast) (mostafa-khairy)


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Hi all,
i'm trying to design a floating point adder using advantage pro and i 
simulating it using modelsim
attached my code
1
LIBRARY ieee;
2
USE ieee.std_logic_1164.all;
3
USE ieee.std_logic_arith.all;
4
5
6
ENTITY fp_adder IS
7
-- Declarations
8
port(a,b: in  std_logic_vector(31 downto 0);
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     c: out std_logic_vector(31 downto 0)
10
  );
11
END fp_adder ;
12
13
-- hds interface_end
14
ARCHITECTURE adder OF fp_adder IS
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--declaration of sign 
16
signal sa,sb,sc: std_logic;
17
--declaration of exponent
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signal tea,teb: std_logic_vector(7 downto 0);
19
signal ea,eb,ec: unsigned(7 downto 0);
20
--declaration of mantissa
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signal tma,tmb: std_logic_vector(22 downto 0);
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signal ma,mb,mc: unsigned(22 downto 0);
23
BEGIN
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--asignement of sign signals
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sa <= a(31);
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sb <= b(31);
27
--assignement of exponent signals
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tea <= std_logic_vector(a(30 downto 23));
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teb <= std_logic_vector(b(30 downto 23));
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ea <= unsigned(tea);
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eb <= unsigned(teb);
32
--assignement of mantissa signals
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tma <= std_logic_vector(a(22 downto 0));
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tmb <= std_logic_vector(b(22 downto 0));
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ma <= unsigned(tma);
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mb <= unsigned(tmb);
37
------------------------------------------------------------------------------------------------------
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process(ea,eb,ec,ma,mb,mc,sa,sb,sc)
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begin
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  if(ea > eb)then loop
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  eb <= eb+1;
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  mb <= '0'& mb(22 downto 1);
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  exit when ea=eb;
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  end loop;
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  mc <= ma+mb;
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  ec <= ea;
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  sc <= sa xor sb;
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  elsif(eb > ea) then loop
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  ea <= ea+1;
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  ma <= '0'& ma(22 downto 1);
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  exit when ea=eb;
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  end loop;
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  mc <= ma+mb;
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  ec <= ea;
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  sc <= sa xor sb;
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  else
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  mc <= ma+mb;
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  ec <= ea;
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  sc <= sa xor sb;
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  end if;
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end process;
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  c(22 downto  0) <= std_logic_vector(mc);
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  c(30 downto 23) <= std_logic_vector(ec);
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  c(31)        <= sc;
65
END adder;

and i found a problem which i couldn't recognize it
there is no error in compiling the code
but at simulation the o/p is UUUUUUUUUUUUUUUUUUUU
1
and there is some warnings at modelsim command window 
2
this is the error massage 
3
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
4
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
5
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
6
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
7
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
8
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
9
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
10
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
11
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
12
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
13
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
14
#    Time: 0 ns  Iteration: 0  Instance: /fp_adder 
15
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
16
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
17
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
18
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
19
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
20
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
21
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
22
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
23
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
24
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
25
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
26
#    Time: 0 ns  Iteration: 1  Instance: /fp_adder 
27
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
28
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
29
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
30
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
31
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
32
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
33
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
34
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
35
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
36
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder 
37
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 
38
#    Time: 0 ns  Iteration: 2  Instance: /fp_adder

could anyone help me to solve this error
is my design synthesizable?

von further on not supported (Guest)


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> could anyone help me to solve this error
This is no error, it is a warning  ;-)
Try default values for your signals:
1
  
2
signal tea,teb: std_logic_vector(7 downto 0) := (others=>'0');
3
signal ea,eb,ec: unsigned(7 downto 0) := (others=>'0');


> is my design synthesizable?
1
  if(ea > eb)then loop
No. Loops like this are not synthesisable.

von Mostafa M. (Company: aast) (mostafa-khairy)


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thanks alot
i do what you suggest it works right when i add 0+0
but the o/p xxxxxxxxxxxx

sorry but could you advice me how to test it

von Duke Scarring (Guest)


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Add default values to all your internal signals.

Duke

von Mostafa M. (Company: aast) (mostafa-khairy)


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this the new vhdl code after add a default value for all internal 
signals
1
LIBRARY ieee;
2
USE ieee.std_logic_1164.all;
3
USE ieee.std_logic_arith.all;
4
5
6
ENTITY fp_adder IS
7
-- Declarations
8
port(a,b: in  std_logic_vector(31 downto 0);
9
     c: out std_logic_vector(31 downto 0)
10
  );
11
END fp_adder ;
12
13
-- hds interface_end
14
ARCHITECTURE adder OF fp_adder IS
15
--declaration of sign 
16
signal sa,sb,sc: std_logic:= '0';
17
--declaration of exponent
18
signal tea,teb: std_logic_vector(7 downto 0):= (others=>'0');
19
signal ea,eb,ec: unsigned(7 downto 0):= (others=>'0');
20
--declaration of mantissa
21
signal tma,tmb: std_logic_vector(22 downto 0):= (others=>'0');
22
signal ma,mb,mc: unsigned(22 downto 0):= (others=>'0');
23
BEGIN
24
--asignement of sign signals
25
sa <= a(31);
26
sb <= b(31);
27
--assignement of exponent signals
28
tea <= std_logic_vector(a(30 downto 23));
29
teb <= std_logic_vector(b(30 downto 23));
30
ea <= unsigned(tea);
31
eb <= unsigned(teb);
32
--assignement of mantissa signals
33
tma <= std_logic_vector(a(22 downto 0));
34
tmb <= std_logic_vector(b(22 downto 0));
35
ma <= unsigned(tma);
36
mb <= unsigned(tmb);
37
------------------------------------------------------------------------------------------------------
38
process(ea,eb,ec,ma,mb,mc,sa,sb,sc)
39
begin
40
  if(ea > eb)then loop
41
  eb <= eb+1;
42
  mb <= '0'& mb(22 downto 1);
43
  exit when ea=eb;
44
  end loop;
45
  mc <= ma+mb;
46
  ec <= ea;
47
  sc <= sa xor sb;
48
  elsif(eb > ea) then loop
49
  ea <= ea+1;
50
  ma <= '0'& ma(22 downto 1);
51
  exit when ea=eb;
52
  end loop;
53
  mc <= ma+mb;
54
  ec <= ea;
55
  sc <= sa xor sb;
56
  else
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  mc <= ma+mb;
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  ec <= ea;
59
  sc <= sa xor sb;
60
  end if;
61
end process;
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  c(22 downto  0) <= std_logic_vector(mc);
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  c(30 downto 23) <= std_logic_vector(ec);
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  c(31)        <= sc;
65
END adder;

i try to test my desig my put
a =.25 "00000000101000000000000000000000"
b =.25 "00000000101000000000000000000000"
so
sa=0
sb=0
sc=0
tea=000000001
teb=000000001
ea=0000000X --i can't understand why?
eb=0000000X --i can't understand why?
tma=01000000000000000000000
tmb=01000000000000000000000
ma=0X000000000000000000000 --i can't understand why?
mb=0X000000000000000000000 --i can't understand why?
mc=XXXXXXXXXXXXXXXXXXXXXXX but i expect to be ="10000000000000000000000"

plz can you explain why there's unknown bits?

von Duke Scarring (Guest)


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Try type conversion without temporary signals, like here:
1
--assignement of exponent signals
2
ea <= unsigned(a(30 downto 23));
3
eb <= unsigned(b(30 downto 23));
4
--assignement of mantissa signals
5
ma <= unsigned(a(22 downto 0));
6
mb <= unsigned(b(22 downto 0));

Duke

P.S.: I suggest to use records:
1
type float_t is record
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  s: std_logic;
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  e: unsigned(7 downto 0);
4
  m: unsigned(22 downto 0);
5
end record;
You can use it like: c.m <= a.m + b.m;

von Andreas S. (andreas) (Admin) Flattr this


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There are some fundamental problems in your code. Is this supposed to be 
a clocked or combinatorial adder? Because at the moment it is neither. 
You have signals that are not assigned in every branch, signals that are 
assigned their previous values, loops with non-constant exit conditions 
- all that will blow up when you try to synthesize it. I suggest you 
follow the rules in http://embdev.net/articles/VHDL and look at some 
examples.

von Ras F. (rasfunk)


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If you just need a FPAdder, try FloPoCo:

http://www.ens-lyon.fr/LIP/Arenaire/Ware/FloPoCo/

It's VERY advanced, you can customize all parameters such as pipeline 
depth, mantissa width, internal representation, ...

What you get is a perfectly synthesizable VHDL entity.

Plus it's free!

von Mostafa M. (Company: aast) (mostafa-khairy)


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@ Andreas Schwarz
thanks for your help but sorry i'm new at vhdl could u explain to me 
what's record and how can i use it i'm trying to read about it from vhdl 
by example but i understand nothing.

@ Ras Funk
thanks alot for your post but i have to do it by myself coz i'll use it 
at my graduation project

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