Hi all, i'm trying to design a floating point adder using advantage pro and i simulating it using modelsim attached my code

1 | LIBRARY ieee; |

2 | USE ieee.std_logic_1164.all; |

3 | USE ieee.std_logic_arith.all; |

4 | |

5 | |

6 | ENTITY fp_adder IS |

7 | -- Declarations |

8 | port(a,b: in std_logic_vector(31 downto 0); |

9 | c: out std_logic_vector(31 downto 0) |

10 | ```
);
``` |

11 | END fp_adder ; |

12 | |

13 | -- hds interface_end |

14 | ARCHITECTURE adder OF fp_adder IS |

15 | --declaration of sign |

16 | signal sa,sb,sc: std_logic; |

17 | --declaration of exponent |

18 | signal tea,teb: std_logic_vector(7 downto 0); |

19 | signal ea,eb,ec: unsigned(7 downto 0); |

20 | --declaration of mantissa |

21 | signal tma,tmb: std_logic_vector(22 downto 0); |

22 | signal ma,mb,mc: unsigned(22 downto 0); |

23 | ```
BEGIN
``` |

24 | --asignement of sign signals |

25 | sa <= a(31); |

26 | sb <= b(31); |

27 | --assignement of exponent signals |

28 | tea <= std_logic_vector(a(30 downto 23)); |

29 | teb <= std_logic_vector(b(30 downto 23)); |

30 | ea <= unsigned(tea); |

31 | eb <= unsigned(teb); |

32 | --assignement of mantissa signals |

33 | tma <= std_logic_vector(a(22 downto 0)); |

34 | tmb <= std_logic_vector(b(22 downto 0)); |

35 | ma <= unsigned(tma); |

36 | mb <= unsigned(tmb); |

37 | ```
------------------------------------------------------------------------------------------------------
``` |

38 | process(ea,eb,ec,ma,mb,mc,sa,sb,sc) |

39 | ```
begin
``` |

40 | if(ea > eb)then loop |

41 | eb <= eb+1; |

42 | mb <= '0'& mb(22 downto 1); |

43 | exit when ea=eb; |

44 | end loop; |

45 | mc <= ma+mb; |

46 | ec <= ea; |

47 | sc <= sa xor sb; |

48 | elsif(eb > ea) then loop |

49 | ea <= ea+1; |

50 | ma <= '0'& ma(22 downto 1); |

51 | exit when ea=eb; |

52 | end loop; |

53 | mc <= ma+mb; |

54 | ec <= ea; |

55 | sc <= sa xor sb; |

56 | ```
else
``` |

57 | mc <= ma+mb; |

58 | ec <= ea; |

59 | sc <= sa xor sb; |

60 | end if; |

61 | end process; |

62 | c(22 downto 0) <= std_logic_vector(mc); |

63 | c(30 downto 23) <= std_logic_vector(ec); |

64 | c(31) <= sc; |

65 | END adder; |

and i found a problem which i couldn't recognize it there is no error in compiling the code but at simulation the o/p is UUUUUUUUUUUUUUUUUUUU

1 | and there is some warnings at modelsim command window |

2 | this is the error massage |

3 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

4 | ```
# Time: 0 ns Iteration: 0 Instance: /fp_adder
``` |

5 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

6 | ```
# Time: 0 ns Iteration: 0 Instance: /fp_adder
``` |

7 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

8 | ```
# Time: 0 ns Iteration: 0 Instance: /fp_adder
``` |

9 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

10 | ```
# Time: 0 ns Iteration: 0 Instance: /fp_adder
``` |

11 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

12 | ```
# Time: 0 ns Iteration: 0 Instance: /fp_adder
``` |

13 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

14 | ```
# Time: 0 ns Iteration: 0 Instance: /fp_adder
``` |

15 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

16 | ```
# Time: 0 ns Iteration: 1 Instance: /fp_adder
``` |

17 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

18 | ```
# Time: 0 ns Iteration: 1 Instance: /fp_adder
``` |

19 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

20 | ```
# Time: 0 ns Iteration: 1 Instance: /fp_adder
``` |

21 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

22 | ```
# Time: 0 ns Iteration: 1 Instance: /fp_adder
``` |

23 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

24 | ```
# Time: 0 ns Iteration: 1 Instance: /fp_adder
``` |

25 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

26 | ```
# Time: 0 ns Iteration: 1 Instance: /fp_adder
``` |

27 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

28 | ```
# Time: 0 ns Iteration: 2 Instance: /fp_adder
``` |

29 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

30 | ```
# Time: 0 ns Iteration: 2 Instance: /fp_adder
``` |

31 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

32 | ```
# Time: 0 ns Iteration: 2 Instance: /fp_adder
``` |

33 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

34 | ```
# Time: 0 ns Iteration: 2 Instance: /fp_adder
``` |

35 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

36 | ```
# Time: 0 ns Iteration: 2 Instance: /fp_adder
``` |

37 | ```
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
``` |

38 | ```
# Time: 0 ns Iteration: 2 Instance: /fp_adder
``` |

could anyone help me to solve this error is my design synthesizable?