#include <avr/io.h>

#include <stdlib.h>

#include <avr/interrupt.h>

#define F_CPU 10000000UL

#include <util/delay.h>

#define RF_PORT  PORTB

#define RF_DDR  DDRB

#define RF_PIN  PINB

#define DDR_IN      0

#define DDR_OUT    1

#define PORT_SEL  PORTB

#define PIN_SEL    PINB

#define DDR_SEL    DDRB

#define  PORT_SDI  PORTB

#define PIN_SDI    PINB

#define DDR_SDI    DDRB

#define PORT_SCK  PORTB

#define PIN_SCK    PINB

#define DDR_SCK    DDRB

#define PORT_NIRQ  PORTB

#define PIN_NIRQ  PINB

#define DDR_NIRQ  DDRB

#define SCK    7  // SCK,  -> RF02

#define NIRQ    6  // nIRQ, -> RF02

#define SDI    5  // SDI,  -> RF02

#define SEL    4  // nSEL, -> RF02

#define DATA   3  // FSK,  -> RF02

#define SEL_OUTPUT()   DDR_SEL  |= (1<<SEL)

#define HI_SEL()    PORT_SEL |= (1<<SEL)

#define LOW_SEL()    PORT_SEL &=~(1<<SEL)

#define SDI_OUTPUT()  DDR_SDI  |= (1<<SDI)

#define HI_SDI()    PORT_SDI |= (1<<SDI)

#define LOW_SDI()    PORT_SDI &=~(1<<SDI)

#define NIRQ_INPUT()  DDR_NIRQ  &=~(1<<NIRQ)

#define NIRQ_HI()    PIN_NIRQ&(1<<NIRQ)

#define SCK_OUTPUT()  DDR_SCK  |=(1<<SCK)

#define HI_SCK()    PORT_SCK |=(1<<SCK)

#define LOW_SCK()    PORT_SCK &=~(1<<SCK)

unsigned int RFXX_WRT_CMD( unsigned int aCmd) {  // to send commands

  unsigned char i;

  unsigned int temp;

  LOW_SCK();  // reset bit SCK

  LOW_SEL();    // reset bit SEL

  for(i=0;i<16;i++)

    {

    temp<<=1;  // temp=temp<<1;

    if(NIRQ_HI()) {  

    temp|=0x0001; // temp is a 16-bit integer

    }

  LOW_SCK();  // reset bit SCK

    if(aCmd&0x8000) {  // if((aCmd&0x8000)==0x8000)

    HI_SDI();  // set bit SDI

    }

    else {

      LOW_SDI();// reset bit SDI

    }

      HI_SCK();  // set bit SCK to shift data from SDI pin to RFM

      aCmd<<=1; // aCmd=aCmd<<1

  }

  LOW_SCK();  // reset bit SCK

  HI_SEL();    // set bit SEL

  return(temp);

}

void RF02B_SEND(unsigned char aByte) {  // send a byte

  unsigned char i;

  for(i=0;i<8;i++)

    {

  while(NIRQ_HI());  // polling nIRQ

  while(!(NIRQ_HI()));

  if(aByte&0x80)

    {

      PORTB|=(1<<DATA);  // set bit(FSK): request data input

    }

    else {

    PORTB&=~(1<<DATA);  // reset bit(FSK): request data input

      }

    aByte<<=1;  // aByte=aByte<<1

  }

}

void RFXX_PORT_INIT(void) { // initialise all neccesary ports

  HI_SEL();    // set bit SEL

  HI_SDI();    // set bit SDI

  LOW_SCK();  // reset bit SCK

  SEL_OUTPUT();  // set port SEL as output

  SDI_OUTPUT(); // set port SDI as output

  NIRQ_INPUT();  // set port SDO as input

  SCK_OUTPUT(); // set port SCK as output

}

void Send (unsigned int byte) {

  unsigned int i, j, ChkSum;

  ChkSum=0;

  RF02B_SEND(0xAA); // PREAMBLE

  RF02B_SEND(0xAA); // PREAMBLE

  RF02B_SEND(0xAA); // PREAMBLE

  RF02B_SEND(0x54); // Sync byte

  RF02B_SEND(byte);  // Data0

  ChkSum+=byte;

  RF02B_SEND(byte);  // Data1

  ChkSum+=byte;

  RF02B_SEND(byte);  // Data2

  ChkSum+=byte;

  RF02B_SEND(byte);  // Data3

  ChkSum+=byte;

  RF02B_SEND(byte);  // Data4

  ChkSum+=byte;

  RF02B_SEND(byte);  // Data5

  ChkSum+=byte;

  RF02B_SEND(byte);  // Data6

  ChkSum+=byte;

  RF02B_SEND(byte);  // Data7

  ChkSum+=byte;

  RF02B_SEND(ChkSum);// Data8

  RF02B_SEND(0xAA);  // dummy byte

  RFXX_WRT_CMD(0xC401);  // (8) TX off

  for(i=0;i<5000;i++)

  for(j=0;j<123;j++);

}

void main(void) {

  RFXX_PORT_INIT();  // initialise all neccesary ports

  RFXX_WRT_CMD(0xCC00); // read internal status register content

  RFXX_WRT_CMD(0x9731); // (2) 

            // b1=1,d1=1,d0=1,x1=1,x0=1,m0=1

            // CLK freq 10MHz

            // Band 868MHz 

            // 10pF

            // 60kHz deviation

  RFXX_WRT_CMD(0xC031); // (3) 

               // ex=1,es=1,dc=1

              // enable crystal oscillator

            // enable synthesizer

            // disable CLK pin

            // POWER AMPLIFY aanzetten?

  RFXX_WRT_CMD(0xA640); // (4) 868MHz ( 860MHz + 6MHz )

  RFXX_WRT_CMD(0xC823); // (5) 4.8kbps 0xC823 << nog delen door 2 (0xD040)

              // r6=1,r2=1,r1=1,r0=1

  RFXX_WRT_CMD(0xB000); // (6) no relative power output

  RFXX_WRT_CMD(0xC220); // (7) ebs=1

               // enable TX sync

  RFXX_WRT_CMD(0xC464); // (8) TX off after 10us (0xC464)

  PORTB|=(1<<DATA);    // set bit FSK

  DDRB|=(1<DATA);    // set port FSK as output

while(1) {

  for( int i=0;i<=50;i++)

  Send(0x0F);

  for( int i=0;i<=50;i++)

  Send(0xF0);

  }

}