1 | #include <avr/io.h>
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2 | #include <stdlib.h>
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3 | #include <avr/interrupt.h>
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4 | #define F_CPU 10000000UL
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5 | #include <util/delay.h>
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6 | #define RF_PORT PORTB
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7 | #define RF_DDR DDRB
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8 | #define RF_PIN PINB
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9 | |
10 | #define DDR_IN 0
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11 | #define DDR_OUT 1
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12 | |
13 | #define PORT_SEL PORTB
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14 | #define PIN_SEL PINB
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15 | #define DDR_SEL DDRB
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16 | |
17 | #define PORT_SDI PORTB
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18 | #define PIN_SDI PINB
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19 | #define DDR_SDI DDRB
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20 | |
21 | #define PORT_SCK PORTB
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22 | #define PIN_SCK PINB
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23 | #define DDR_SCK DDRB
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24 | |
25 | #define PORT_NIRQ PORTB
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26 | #define PIN_NIRQ PINB
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27 | #define DDR_NIRQ DDRB
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28 | |
29 | #define SCK 7 // SCK, -> RF02
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30 | #define NIRQ 6 // nIRQ, -> RF02
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31 | #define SDI 5 // SDI, -> RF02
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32 | #define SEL 4 // nSEL, -> RF02
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33 | #define DATA 3 // FSK, -> RF02
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34 | |
35 | |
36 | #define SEL_OUTPUT() DDR_SEL |= (1<<SEL)
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37 | #define HI_SEL() PORT_SEL |= (1<<SEL)
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38 | #define LOW_SEL() PORT_SEL &=~(1<<SEL)
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39 | |
40 | #define SDI_OUTPUT() DDR_SDI |= (1<<SDI)
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41 | #define HI_SDI() PORT_SDI |= (1<<SDI)
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42 | #define LOW_SDI() PORT_SDI &=~(1<<SDI)
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43 | |
44 | #define NIRQ_INPUT() DDR_NIRQ &=~(1<<NIRQ)
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45 | #define NIRQ_HI() PIN_NIRQ&(1<<NIRQ)
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46 | |
47 | #define SCK_OUTPUT() DDR_SCK |=(1<<SCK)
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48 | #define HI_SCK() PORT_SCK |=(1<<SCK)
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49 | #define LOW_SCK() PORT_SCK &=~(1<<SCK)
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50 | |
51 | |
52 | unsigned int RFXX_WRT_CMD( unsigned int aCmd) { // to send commands
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53 | |
54 | unsigned char i;
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55 | unsigned int temp;
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56 | |
57 | LOW_SCK(); // reset bit SCK
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58 | LOW_SEL(); // reset bit SEL
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59 | for(i=0;i<16;i++)
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60 | {
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61 | temp<<=1; // temp=temp<<1;
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62 | if(NIRQ_HI()) {
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63 | temp|=0x0001; // temp is a 16-bit integer
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64 | }
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65 | LOW_SCK(); // reset bit SCK
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66 | if(aCmd&0x8000) { // if((aCmd&0x8000)==0x8000)
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67 | HI_SDI(); // set bit SDI
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68 | }
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69 | else {
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70 | LOW_SDI();// reset bit SDI
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71 | }
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72 | HI_SCK(); // set bit SCK to shift data from SDI pin to RFM
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73 | aCmd<<=1; // aCmd=aCmd<<1
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74 | }
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75 | LOW_SCK(); // reset bit SCK
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76 | HI_SEL(); // set bit SEL
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77 | return(temp);
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78 | }
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79 | |
80 | |
81 | void RF02B_SEND(unsigned char aByte) { // send a byte
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82 | |
83 | unsigned char i;
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84 | |
85 | for(i=0;i<8;i++)
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86 | {
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87 | while(NIRQ_HI()); // polling nIRQ
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88 | while(!(NIRQ_HI()));
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89 | if(aByte&0x80)
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90 | {
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91 | PORTB|=(1<<DATA); // set bit(FSK): request data input
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92 | }
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93 | else {
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94 | PORTB&=~(1<<DATA); // reset bit(FSK): request data input
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95 | }
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96 | aByte<<=1; // aByte=aByte<<1
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97 | }
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98 | }
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99 | |
100 | |
101 | void RFXX_PORT_INIT(void) { // initialise all neccesary ports
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102 | HI_SEL(); // set bit SEL
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103 | HI_SDI(); // set bit SDI
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104 | LOW_SCK(); // reset bit SCK
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105 | SEL_OUTPUT(); // set port SEL as output
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106 | SDI_OUTPUT(); // set port SDI as output
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107 | NIRQ_INPUT(); // set port SDO as input
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108 | SCK_OUTPUT(); // set port SCK as output
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109 | }
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110 | |
111 | |
112 | void Send (unsigned int byte) {
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113 | |
114 | unsigned int i, j, ChkSum;
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115 | |
116 | ChkSum=0;
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117 | RF02B_SEND(0xAA); // PREAMBLE
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118 | RF02B_SEND(0xAA); // PREAMBLE
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119 | RF02B_SEND(0xAA); // PREAMBLE
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120 | RF02B_SEND(0x54); // Sync byte
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121 | RF02B_SEND(byte); // Data0
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122 | ChkSum+=byte;
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123 | RF02B_SEND(byte); // Data1
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124 | ChkSum+=byte;
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125 | RF02B_SEND(byte); // Data2
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126 | ChkSum+=byte;
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127 | RF02B_SEND(byte); // Data3
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128 | ChkSum+=byte;
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129 | RF02B_SEND(byte); // Data4
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130 | ChkSum+=byte;
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131 | RF02B_SEND(byte); // Data5
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132 | ChkSum+=byte;
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133 | RF02B_SEND(byte); // Data6
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134 | ChkSum+=byte;
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135 | RF02B_SEND(byte); // Data7
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136 | ChkSum+=byte;
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137 | RF02B_SEND(ChkSum);// Data8
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138 | RF02B_SEND(0xAA); // dummy byte
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139 | |
140 | RFXX_WRT_CMD(0xC401); // (8) TX off
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141 | |
142 | for(i=0;i<5000;i++)
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143 | for(j=0;j<123;j++);
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144 | }
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145 | |
146 | void main(void) {
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147 | |
148 | RFXX_PORT_INIT(); // initialise all neccesary ports
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149 | |
150 | RFXX_WRT_CMD(0xCC00); // read internal status register content
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151 | |
152 | RFXX_WRT_CMD(0x9731); // (2)
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153 | // b1=1,d1=1,d0=1,x1=1,x0=1,m0=1
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154 | // CLK freq 10MHz
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155 | // Band 868MHz
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156 | // 10pF
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157 | // 60kHz deviation
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158 | |
159 | RFXX_WRT_CMD(0xC031); // (3)
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160 | // ex=1,es=1,dc=1
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161 | // enable crystal oscillator
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162 | // enable synthesizer
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163 | // disable CLK pin
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164 | // POWER AMPLIFY aanzetten?
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165 | |
166 | RFXX_WRT_CMD(0xA640); // (4) 868MHz ( 860MHz + 6MHz )
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167 | |
168 | RFXX_WRT_CMD(0xC823); // (5) 4.8kbps 0xC823 << nog delen door 2 (0xD040)
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169 | // r6=1,r2=1,r1=1,r0=1
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170 | |
171 | RFXX_WRT_CMD(0xB000); // (6) no relative power output
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172 | |
173 | RFXX_WRT_CMD(0xC220); // (7) ebs=1
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174 | // enable TX sync
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175 |
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176 | RFXX_WRT_CMD(0xC464); // (8) TX off after 10us (0xC464)
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177 | |
178 | PORTB|=(1<<DATA); // set bit FSK
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179 | DDRB|=(1<DATA); // set port FSK as output
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180 | |
181 | |
182 | while(1) {
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183 | for( int i=0;i<=50;i++)
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184 | Send(0x0F);
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185 | for( int i=0;i<=50;i++)
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186 | Send(0xF0);
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187 | }
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188 | }
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