Search results for "scrambler"

error hdl compiler 164 Locked

- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity scrambler is Port ( e : in STD_LOGIC_VECTOR (29 downto 0); Sel : in STD_LOGIC_VECTOR (3 downto 0); s : out STD_LOGIC_VECTOR (29 downto 0)); end scrambler; architecture Behavioral of scrambler is SIGNAL

with Project navigator ISE is : ERROR:HDLParsers:164 - "C:/Users/PROXIMEDIA/Documents/ISE-file/scrambler/scrambler.vhd" Line 93. parse error, unexpected IDENTIFIER please help me

FPGA, VHDL & Verilog ·ISE xilinx ·2013-08-21 23:10 ·11 Replies

timing constraint

""ERROR:HDLParsers:3305 - "C:/Users/PROXIMEDIA/Documents/ISE-file/scrambler/scrambler.vhd" Line 301. The actual value (Signal 'widthWCDMA') associated with a generic must be a globally static expression."" How shall we do it?

ranges that should or must be static when synthesizing the design... BTW: by reading the word "scrambler" i become kind of suspicious: http://embdev.net/search?query=scrambler

FPGA, VHDL & Verilog ·ISE xilinks ·2013-08-26 22:17 ·2 Replies

generic register lfsr

IEEE.STD_LOGIC_ARITH.ALL; use IEEE.NUMERIC_STD.ALL; use STD.TEXTIO.ALL; library WORK; use WORK.pkgg.ALL; entity scrambler is Port ( e : in STD_LOGIC_VECTOR (29 downto 0); Sel : in STD_LOGIC_VECTOR (3 downto 0); s : out STD_LOGIC_VECTOR (29 downto 0)); end scrambler; architecture Behavioral of scrambler is SIGNAL rst_n : std_logic; SIGNAL clk : std_logic; SIGNAL dout : std_logic_vector(29 downto 0); CONSTANT width : integer := 30; CONSTANT length : integer

FPGA, VHDL & Verilog ·siwar ·2013-09-23 22:04 ·4 Replies

scrambler/descrambler vhdl code

good morning Please I would a vhdl code for scrambler/descrambler which takes as parameter binary data and the scrambler polynomial generator with its intial sequence. Also I would a code for a double polynomial generator for example UMTS had two polynomial generator : P1 (X) = X^17 + X^7 + 1 P2 (X) = X^17 + X^10 + X^7 + X^5 + 1 it joined a scrambler/descrambler matlab code which polynomial generator is P (X) = 1 + X^5 + X^12 + X^16 Thx in advance

FPGA, VHDL & Verilog ·siwar dammak ·2013-06-24 08:56 ·2 Replies

error : Cannot drive signal 'e' of mode IN

Good morning I have an error on my vhdl file, I would affect e to one of my component list (scramblerUMTS, scramblerGSM, etc...) when sel is 000 or 0001 etc... please I need a reply tnx

FPGA, VHDL & Verilog ·siwar dammak ·2013-06-05 13:11 ·9 Replies

fatal vhdl error

Iteration: 0 Process: /composantscrambler/line__332 File: C:/modeltech_10.0c/examples/composant-scrambler.vhd # Fatal error in Process line__332 at C:/modeltech_10.0c/examples/composant-scrambler.vhd line 341 it joined my vhdl program thanks

FPGA, VHDL & Verilog ·entity / package ·2013-07-14 17:07 ·2 Replies

GPS to FPGA to PC

-3 characters manually, that may tell you what you have to fix. yes you true, i have receive scramble data, and data not constants per second

enough. But: clk9600 ist NOT a clock, is is just a simple clock enable... > i have receive scramble data, and data not constants per second As I saw that code my first thought was: Ouch! You MUST implement a test bench an check your design on that test bench. Then you can see that whole bunch

FPGA, VHDL & Verilog ·Yuniarto Wimbo Nugroho ·2016-02-03 09:30 ·9 Replies

variable vhdl

Iteration: 0 Process: /composantscrambler/line__320 File: C:/modeltech_10.0c/examples/composant-scrambler.vhd # Fatal error in Process line__320 at C:/modeltech_10.0c/examples/composant-scrambler.vhd line 339) because I fixed s to std_logic_vector (29 downto 0) then it take differen value (doutIS95

FPGA, VHDL & Verilog ·siwar dammak ·2013-07-19 17:27 ·2 Replies

OpenHR20: Firmware for Honeywell Rondostat HR20E

dario that attacker could see enc(rand). so i putted a rand2 on start of message in 2 which will scramble all the rest of the packet (->CFB mode) (lesson learnd ;) beside, even if the attacker could catch a rand/enc(rand)-pair, then he couldnt offline-calc the key: rand is shorter than the key so many

µC & Digital Electronics ·Mario Fischer ·2022-11-26 13:30 ·1121 Replies