Search results for "111"

ERSA 111 ms60

for you! You can find (German language) an interesting article regarding the substitution of ERSA111 IC, and the solution seems very simple ERSA111==LM324! The link is: https://www.fingers-welt.de/phpBB/viewtopic.php?t=7438 I hope this may be helpful for you best pienne

> ... the solution seems very simple ERSA111==LM324 Ouch. After five years, just for the records: https://www.mikrocontroller.net/topic/544326#new

Analog Circuits ·Guilherme Lopes ·2022-10-19 16:46 ·7 Replies

VHDL project : 5 bit shift reg

110" (6). what should happen with every rising clock? data <= ? And what should happen if SEL = "111" (7)?

complement when others => data <= std_logic_vector(unsigned(not data) +1); --2s' complement (SEL = "111")[/vhdl]

FPGA, VHDL & Verilog ·Michael ·2017-04-24 13:54 ·42 Replies

Active-HDL design

0.0 then report "2. remainder is zero!"; end if; j := 111.1; if a=a*j/111.1 then report "b) equal!"; else report "b) different!"; end if; if a*j/111.1 mod 1.0 = 0.0 then report "3. remainder is zero!"; end if; j:=a*j/111.1 mod 1.0; report "Should be .0 --> " & real'image(j); end process; end; [/vhdl] Think about the results...

FPGA, VHDL & Verilog ·Nazar Rendzenyak ·2015-12-17 08:12 ·34 Replies

Implementation of MASH 111 in verilog

I am trying to design MASH 111 DDSM using verilog. I have attatched the code. But output is "xxx" always. Can someone help?

FPGA, VHDL & Verilog ·GAURAV G. ·2020-05-17 08:51 ·1 Replies

Verilog circuit

b and c connected at the bottom of the MUX? The left input is b, then a and right is c. So 000 ... 111 is a combination of b, a, c. In VHDL it would be: signal sel := std_logic_vector(2 downto 0); begin sel <= b & a & c; with sel select y <= a and b when "000", c when "001

3'b111: y = a ^ b; endcase end assign sel = b & a & c;

FPGA, VHDL & Verilog ·Mattia ·2023-03-27 17:52 ·4 Replies

decoder in vhdl dont work in simulation.

then f<="00000100" after 1 ps; elsif a="110" then f<="00000010" after 1 ps; elsif a="111" then f<="00000001" after 1 ps; else null; end if; end if; end process; end bhv; [/vhdl]

010" after 20ns, "011" after 30ns, "100" after 40ns, "101" after 50ns, "110" after 60ns, "111" after 70ns, "000" after 80ns, "001" after 90ns, "010" after 100ns, "011" after 110ns, "100" after 120ns, "101" after 130ns, "110" after 140ns, "111" after 150ns; END; [/vhdl]

FPGA, VHDL & Verilog ·ee_vhdl ·2019-01-07 13:47 ·5 Replies

Display 640x480 Nexys 3 board

--------------------------------------- if hcounter < 640 and vcounter < 480 then red<= "111"; green<="111"; blue<="11"; hsync<='1'; vsync<='0'; else red<= "111"; green<="111"; blue<="11"; hsync<='1'; vsync<='0'; end if; ----------

FPGA, VHDL & Verilog ·sketchy ·2014-10-15 18:57 ·8 Replies

Internal signals in vhdl

ms; pon_rst_n <= '0'; wait for 5 ms; pon_rst_n <= '1'; wait for 5 ms; ifc_a27_31 <= "111"; wait; end process; end; [/vhdl]

pon_rst_n <= '0'; wait for 5 ms; pon_rst_n <= '1'; wait for 5 ms; ifc_a27_31 <= "111"; ifc_ad0_7 <= "ZZZ"; BD_SEL_PLD <= '1'; HS_PG00D_PLD <= '0'; HS_FLT_PLD <= '0'; ifc_cs3_n <= '0'; -- low active ifc_oe_n <= '0'; -- low active ifc_we_n <

FPGA, VHDL & Verilog ·Hareesh Mohanan ·2017-08-25 18:42 ·7 Replies

How to instantiate another vhd file inside testbench, where the testbench is used for opening files

component* of your testbench. And the testbench manages the interconnets between the ReadFile and lab111 *components*.

testbenches should not have entities, i created a new testbench, instantiated both the ReadFile and Lab111 as components, make the necessary port and generic maps & was finally able to load the data into the testbench. Thanks again. Best of Regards, Zahid.

FPGA, VHDL & Verilog ·Zahid ·2024-01-07 23:21 ·4 Replies

Lookup Table doesnt work

122,122,121,121,121,120,120,120,119,119,119,119,118,118,118,117,117,117,116,116,116,116,115,115, 115,114,114,114,114,113,113,113,113,112,112,112,111,111,111,111,110,110,110,110,109,109,109,109, 108,108,108,108,107,107,107,107,107,106,106,106,106,105,105,105,105,104,104,104,104,104,103,103, 103,103,102,102,102,102,102,101,101,101,101,101,100,100,100,100,100,998,996,994,992,990,988,987

µC & Digital Electronics ·Lea ·2011-03-12 22:48 ·3 Replies

Integer Assignment to STD_LOGIC_VECTOR

: o=8’d1; In my VHDL case statement I could come up with the below assignment case d is when "111" => o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8)); Is there an easier way of doing the same without using Type conversions in VHDL. Something like the code below (Although this will return a compile error

#5221815: > In my VHDL case statement I could come up with the below assignment > case d is > when "111" => o <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,8)); > > Is there an easier way of doing the same without using Type conversions > in VHDL. There are literals in VHDL. It's either like x"1" or 16#1#. You

FPGA, VHDL & Verilog ·Rejoy Mathews ·2017-11-26 22:18 ·3 Replies

For loop in VHDL

when "001" => aluout <= srca or srcb; when "010"|"110" => aluout <= sum; when "111" => aluout <= (0 => sum(31), others => '0'); when others => aluout <= (others => 'X'); end case; end process; zero <= '1' when (aluout = X"00000000") else '0'; dataadr <=

when "001" => aluout <= srca or srcb; when "010"|"110" => aluout <= sum; when "111" => aluout <= (0 => sum(31), others => '0'); when others => aluout <= (others => 'X'); end case; end process; zero <= '1' when (aluout = X"00000000") else '0'; dataadr <=

FPGA, VHDL & Verilog ·Chris Regform ·2015-04-13 02:17 ·5 Replies

Verilog VGA code HS VS timing

vc >34 && vc < 515) begin if (hc > 143 && hc < 700) begin red = 3'b111; green = 3'b000; blue= 2'b00; end end end endmodule Plus , ucf file: CE: Start of Constraints generated by PACE #PACE: Start of PACE I/O

vc >34 && vc < 515) > begin > if (hc > 143 && hc < 700) > begin > red = 3'b111; > green = 3'b000; > blue= 2'b00; > end [code] else red = ... else red = [/code]

FPGA, VHDL & Verilog ·Keny Joneyer ·2016-01-06 17:48 ·7 Replies

coding the vga port

- 803 = Sync-pulse + Back-porch + Visible-area then if bin = '1' then red_out <= "111"; green_out <= "111"; blue_out <= "11"; elsif bin = '0' then red_out <= "000"; green_out <= "000"; blue_out <= "00"; end if; else red_out <

FPGA, VHDL & Verilog ·keith dunc ·2013-02-12 08:12 ·6 Replies

Siemens TBB206G CMOS PLL synthesizer integrated circuit

needs 22 bits. The last 3 bits contain the target address. In dual modulus mode this bits have to be 111. N/A divider in binary: 0010 1010 0011 1010 1101 1110. First and last bit is always 0. Bits 2...8 contain the value of divider A and bits 9...23 that of divider N. Divider A = 42 Divider

bits. The > last 3 bits contain the target address. In dual modulus mode this bits > have to be 111. > > N/A divider in binary: 0010 1010 0011 1010 1101 1110. > > First and last bit is always 0. Bits 2...8 contain the value of divider > A and bits 9...23 that of divider N. > > Divider A

µC & Digital Electronics ·Dang Huynh ·2021-09-05 13:46 ·5 Replies

help with uart

shift_counter == 4'b1000 || shift_counter == 4'b1111) begin SR_2 <= SR_2 +1; end if(counter8ciklov < 3'b111 && SR_2 == 2'b01)begin counter8ciklov <= counter8ciklov +1; end else begin if(counter8ciklov ==3'b111 && SR_2 == 2'b01)begin SR_2 <= SR_2 +2; counter8ciklov <= 0; end end end always @(posedge

FPGA, VHDL & Verilog ·PEter ·2024-01-17 17:25 ·12 Replies

control logic for memory selection

eg:if control signal is 00 memory1 is selected and my address counter starts counting from 000 to 111 (data also sent in parellel)...once complete....then sample next control signal for writing memory2...

previous control signal is generated....ie if i select ctrl to be 00 then addr counts from 000 to 111 even if ctrl changes in between it does not matter..

FPGA, VHDL & Verilog ·felix89 ·2016-02-24 16:32 ·2 Replies

Variable clock with prescaler?

clock_out <= div(5); elsif (controlfreq <= "110") then clock_out <= div(6); elsif (controlfreq <= "111") then clock_out <= div(7); end if; end process; end bhv; [/vhdl]

<= div(5); > elsif (controlfreq <= "110") then > clock_out <= div(6); > elsif (controlfreq <= "111") then > clock_out <= div(7); I suggest to use the case-construct here. See: https://en.wikibooks.org/wiki/Programmable_Logic/VHDL_Sequential_Statement https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design

FPGA, VHDL & Verilog ·Mohamed H. ·2019-05-17 09:01 ·2 Replies

Where is the fatal error? I couldnt find it

you have to give every value the correct 4bit. If the int is 9 (1001) so the Segments are all on (111 1111). How is it decided what time is the alarm time? Does the current time just count up from 0 to 9?

FPGA, VHDL & Verilog ·Engin ·2022-07-29 16:09 ·14 Replies

car taillights

left2on : std_logic_vector(3 downto 1) := "011"; CONSTANT left3on : std_logic_vector(3 downto 1) := "111"; CONSTANT rightoff : std_logic_vector(3 downto 1) := "000"; CONSTANT right1on : std_logic_vector(3 downto 1) := "100"; CONSTANT right2on : std_logic_vector(3 downto 1) := "110"; CONSTANT right3on : std_logic_vector(3 downto 1) := "111"; signal sclk: std_logic; BEGIN DIVIDER : entity work.clock_divider(behavior) generic map (DIVISOR => DIVISOR) port map (clk => clk, rst => rst, q => sclk); clocked : PROCESS(sclk,rst

FPGA, VHDL & Verilog ·Dfd D. ·2019-12-04 18:11 ·2 Replies

Syntax Help with Project

"001" => tempLED <="011"; when "010" => tempLED <="000"; when "011" => tempLED <="111"; when others => tempLED <= "000"; end case; end if; end process; led_out <= tempLED; end balls_arch; library IEEE; use ieee.std_logic_1164.all; entity Baseball

"001" => tempLED <="011"; when "010" => tempLED <="000"; when "011" => tempLED <="111"; when others => tempLED <= "000"; end case; end if; end process; led_out <= tempLED; end ball_arch; library IEEE; use ieee.std_logic_1164.all; entity

FPGA, VHDL & Verilog ·Annon ·2014-11-27 04:37 ·2 Replies

Counter in verilog

pulse it is 101 then output should be as follows: counter1 000,001,010,011,100,101,110,111, 000,001,.. counter2 011,100,101,110,111,000,001,010, 101,110,.. The code which I tried for that is as follows but not got the correct result ,so please help me to find out the mistake

FPGA, VHDL & Verilog ·Nisarg Shah ·2013-12-27 09:42 ·0 Replies

HELP call VHDL code to other VHDL code

IF (cnt = "1111111111111111111111") THEN state <= "111"; END IF; IF (clk_div2 /= xi) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE

out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN "111" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "000";

FPGA, VHDL & Verilog ·Vicky Vicky ·2012-04-15 16:44 ·3 Replies

OpenHR20: Firmware for Honeywell Rondostat HR20E

CTL_creditExpiration; extern int32_t lastTempChangeSumError; extern uint8_t average_sumerr_count; motor.c: 111 CTL_integratorBlock=CTL_INTEGRATOR_BLOCK; watch.c: /* 00 */ ((uint16_t) &sumError) + B16, /* 01 */ ((uint16_t) &CTL_integratorBlock) + B8, /* 02 */ ((uint16_t) &CTL_interatorCredit

folder. now after inserting the batteries there is a bunch of bytes received 170 177 125 053 035 111 091 155 159 191 115 053 059 191 155 159 157 157 191 159 157 139 153 143 139 ..... display shows version 1.0 (last time it said 0.99) any hints? baudrate 9600 stop1 no parity is the voltage

µC & Digital Electronics ·Mario Fischer ·2022-11-26 13:30 ·1121 Replies

PS2 Keyboard and RAM block interaction Verilog

case (hex_digit) 4'h0: segments = 7'b100_0000; 4'h1: segments = 7'b111_1001; 4'h2: segments = 7'b010_0100; 4'h3: segments = 7'b011_0000; 4'h4: segments = 7'b001_1001; 4'h5: segments = 7'b001_0010; 4'h6: segments = 7'b000_0010; 4'h7: segments = 7'b111_1000; 4'h8: segments = 7'b000_0000; 4'h9: segments = 7'b001_1000; 4'hA: segments = 7'b000_1000; 4'hB: segments = 7'b000_0011; 4'hC: segments

FPGA, VHDL & Verilog ·Sarah ·2016-11-20 23:17 ·1 Replies

error (12007) top-level design entity "projet" is undefined

111

FPGA, VHDL & Verilog ·Lpsyco Lpsyco ·2022-07-27 16:28 ·5 Replies

Please help for 4-bit ALU

'1' if (A + B + Cin) > $F else '0' 110 | SUB | |A - B| |'1' if (A < B), else '0' 111 | SBC | |Cin + A-B| |'1' if (A + Cin) < B, else '0' [Zero <= '1' if Output is 0, else '0'] Can someone please help me write a VHDL code for that ALU, You can find attached the

FPGA, VHDL & Verilog ·peres Z. ·2012-07-05 09:57 ·6 Replies

I don't really understand how VGA controlling works

from submodules that decides the "shapes" of objects on screen 3'b ??1: VGA_RGB <= 3'b 111; //white snow 3'b ?10: VGA_RGB <= (color_flag) ? (3'b 110) : (3'b 111); //switching between yellow and white 3'b 100: VGA_RGB <= 3'b 010; //green tree

FPGA, VHDL & Verilog ·Naketo Ito ·2015-12-29 18:54 ·0 Replies

Help with VHDL code

ELSIF FO = 101 THEN SOUT <= -BI; ELSIF FO = 110 THEN SOUT <= AI + 1; ELSIF FO = 111 THEN SOUT <= AI - 1; END IF; END PROCESS; END FUNCTION8; I guess what Im really asking is do you see anything wrong with the code?? where did I go wrong?? Any suggestions on some

FPGA, VHDL & Verilog ·Eddie Pena ·2013-01-29 18:30 ·9 Replies

SDRAM Memory Controller for Terasic DE0-nano

s_init_pre; n.address(10) <= '1'; end if; -- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then n.state <= s_init_ref;

FPGA, VHDL & Verilog ·jeorges FrenchRivera ·2015-03-20 14:19 ·6 Replies

3 bit output

already designed it. But, the problem is I can't get that desired output I want. I got 000, 001, 011 and 111 outputs. Here I attach my code and testbench and also Isim simulator waveform part. Thank you.

FPGA, VHDL & Verilog ·Ashuuu ·2016-05-03 22:24 ·3 Replies

VERILOG CODE

output reg match; reg [2:0] mem[7:0]; initial begin mem[0]=3'b110; mem[1]=3'b010; mem[2]=3'b111; mem[3]=3'b000; mem[4]=3'b110; mem[5]=3'b101; mem[6]=3'b011; mem[7]=3'b110; end always@(posedge clk) begin for(i=3'd0;i<8;i=i+1) begin if (in[i]==1'b1) sum=sum ^ mem[i]; end $display

FPGA, VHDL & Verilog ·Akshay E. ·2015-02-06 15:41 ·4 Replies

multiple driver error

if (clk'event and clk='1') then if (en = '1' and rd='1' and wr='1' and s2='1' and count1="111" and s1='0' ) then ... [/vhdl] Due to the incomplete sensitivity list your simnulation ist totally crap. And the description of an asynchronous clock enable is very unusual... :-/ This warning

FPGA, VHDL & Verilog ·rajendra soloni ·2011-04-12 21:12 ·4 Replies

Error in VHDL

when "00100000"=> y<="101"; when "01000000"=> y<="110"; when others=> y<="111"; end case; else y<="UUU"; end if; end process; end enc_arc; [/vhdl] this is my code but i get this error message

FPGA, VHDL & Verilog ·vhdl newbie ·2013-09-10 15:05 ·2 Replies

Bit Bang SPI

SD card. How can I bit bang SPI on ARM? I couldn't find SPI bit bang code specifically for ARM/LPC111x. It is simply using bit bang code for AVR/8051/etc? Thanks in advance, John

µC & Digital Electronics ·John ·2011-04-07 18:25 ·2 Replies

RAM overflow is it acceptable

: 32801 from 26624 -------> 123% Number of 4 input LUTs : 29767 from 26624 -------> 111% Number of bonded IOBs : 33 from 221 -------> 14% Number of GCLKs : 2 from 8 ------->25% ------------------------------------------------------------

FPGA, VHDL & Verilog ·Abdallah      ·2014-04-17 16:26 ·4 Replies

Instruction set implementation in VHDL

constant BEQ : std_logic_vector(2 downto 0) := "110"; constant JALR : std_logic_vector(2 downto 0) := "111"; -- SIGNALS DECLARATION signal opcode : std_logic_vector(MAXWIDTH-1 downto MAXWIDTH-3); signal regA : std_logic_vector(MAXWIDTH-4 downto MAXWIDTH-6); signal regB : std_logic_vector(MAXWIDTH

FPGA, VHDL & Verilog ·Maxim Moor ·2015-11-30 19:01 ·8 Replies

Header for PIC16F688 with C-Compiler

digital pin. I don't see it on this chip. As for the configuration bits (what is set in MPLAB, page 111 of datasheet), make sure the watchdog is disabled for now, WDTE, and set FOSC to binary 100. That sets it to use the internal oscillator. Make sure the MCLR pin is pulled to +5 so it doesn't get stuck

µC & Digital Electronics ·Stefan Hölfer ·2013-05-08 17:33 ·3 Replies

need help to modify my code

data = 8'b11100011; 7'b101: data = 8'b00110011; 7'b110: data = 8'b11110111; 7'b111: data = 8'b00111011; 7'b1000: data = 8'b00110001; 7'b1001: data = 8'b00010000; 7'b1010: data = 8'b00100000; 7'b1011: data = 8'b11101101; 7'b1100: data = 8'

= 8'b11110011; 7'b101: weight = 8'b11100110; 7'b110: weight = 8'b11101100; 7'b111: weight = 8'b11110110; 7'b1000: weight = 8'b11111001; 7'b1001: weight = 8'b00000010; 7'b1010: weight = 8'b11111011; 7'b1011: weight = 8'b00001100; 7'b1100:

FPGA, VHDL & Verilog ·shreyas patel ·2013-12-25 11:44 ·0 Replies

M-Bus via Raspberry: reading out ABB B23 meter

my German post which I unfortunately cannot edit anymore. I need to read data from an ABB "B23 111-101" meter which is accessible via an IR-interface on its left side. This IR-interface is configured to M-Bus, 2400 Bd & Address 9 (arbitrary number). For reading from that IF I am using an IR Read

µC & Digital Electronics ·Moadl ·2020-04-27 12:51 ·4 Replies

Resetting Registers on Digital Clock Manager Output

reg [3 : 0] SR; always @ (posedge CLKIN) begin if(RESET) begin SR [3 : 0] <= 4'b111; LOCKED_R <=0; end else begin LOCKED_R <= LOCKED; if(LOCKED < LOCKED_R | STATUS [1] )// H to L LOCKED | CLKIN UNSTABLE SR <= {1'b1 , SR[3 : 1]}; else SR <= {1'b0 , SR[

FPGA, VHDL & Verilog ·Ahmed Abbasi ·2016-11-21 18:00 ·3 Replies

problems with the at91sam7xc getting started example

..\lowlevel.c:102: error: `AT91C_PMC_MOSCS' undeclared (first use in this function) ..\lowlevel.c:111: error: `AT91C_CKGR_USBDIV_1' undeclared (first use in this function) ..\lowlevel.c:112: error: `AT91C_CKGR_OUT_0' undeclared (first use in this function) ..\lowlevel.c:114: error: `AT91C_CKGR_MUL'

µC & Digital Electronics ·Mark D. ·2008-03-06 09:28 ·4 Replies

problem with sinulation in ISE (FPGA)

VHDL coding itself in each entity. The PN generator for Source 1 is initialized with (S2 S1 S0) = 111 and generates PN code 1110100 whereas the PN generator for Source 2 is initialized with (S2 S1 S0) = 110 and generates PN code1101001. so I wrote the sketch I create two inputs one is( CLOCK )

FPGA, VHDL & Verilog ·Zakariya AL-Mazroo'Ee ·2014-06-28 10:00 ·2 Replies

How to do this please

to bus a The return_out output will only be modified when change has a value different from 3'b111. If change is equal to 3'b100, then the return_out output will be equal to the bus formed by the least significant bits of a and b. If change is equal to 3'b001, then the return_out output will

FPGA, VHDL & Verilog ·Berger ·2024-01-10 11:05 ·5 Replies

does vhdl accept this assignment of bits

first_part[/vhdl] contains the copied bits from the stream, signal flag contain the actual no bits, either 111 for 001 or 11 for 01 and [vhdl]signal second_part[/vhdl] contains the final inverted form. Here, i want to ask that if the do the following, would it achieve my purpose without error: [vhdl] first_part

FPGA, VHDL & Verilog ·Amna Khan ·2014-01-06 21:53 ·3 Replies

Weird warning for my design

SCORE_Inter <= DelIy_i_j_1; //C 3'b110: SCORE_Inter <= LUT; //A 3'b111: SCORE_Inter <= 0; //- (output 0) default: SCORE_Inter <= 0; //- (output 0) endcase end endmodule [/code] Based on the attached waveform,the 1st

FPGA, VHDL & Verilog ·dayana42200 ·2018-09-19 02:34 ·17 Replies

Datapath 8 bits VHDL Modelsim

when "101" => f <= a - b; -- substact when "110" => f <= a + 1; -- increment when "111" => f <= a - 1; -- decrement when others => f <= (others => '0'); end case; end process; end behavior; -- shifter .vhd library ieee ; use ieee.std_logic_1164.all ; entity

FPGA, VHDL & Verilog ·KleinBagel ·2018-10-25 21:29 ·6 Replies

VHDL simulation problem-need experts review

; led<="110"; if(bi < 7) then bi:=bi+1; end if; elsif(cyc=20 ) then ack<=sda; bi:=0; led<="111"; elsif (cyc>=21 and cyc<=28 ) then sda<=data(2)(bi); led<="000"; if(bi < 7) then bi:=bi+1; end if; elsif(cyc=29 ) then ack<=sda; led<="001"; elsif(cyc=30 and count >70) then sda<='1'; led

FPGA, VHDL & Verilog ·Shahul Akthar ·2010-07-07 07:15 ·1 Replies

compilation error

Error: ex4.vhd(89): Nonresolved signal 'sel_mux' has multiple sources. # Drivers: # ex4.vhd(111):Statement MUX_DFF # ex4.vhd(96):Conditional signal assignment line__96 # ** Error: ex4.vhd(139): VHDL Compiler exiting # D:/Modeltech_pe_edu_10.2a/win32pe_edu/vcom failed. thanks in advance

FPGA, VHDL & Verilog ·amitai ·2013-05-16 07:24 ·5 Replies

ADC on DEO NANO not working

rising_edge(CLK_50); rst_btn_sr <= rst_btn_sr(1 downto 0) & (NOT BTN_RST); if (rst_btn_sr = "111") then reset_me <= '1'; else reset_me <= '0'; end if; end process reset_btn_proc; --RESET process reset_proc :process begin wait until rising_edge(CLK

FPGA, VHDL & Verilog ·chinmaye ·2018-04-25 01:22 ·3 Replies