fatal vhdl error
Guest
#3240390
good morning what mean this error # ** Fatal: (vsim-3420) Array lengths do not match. Left is 30 (29 downto 0). Right is 14 (13 downto 0). # Time: 0 ns Iteration: 0 Process: /composantscrambler/line__332 File: C:/modeltech_10.0c/examples/composant-scrambler.vhd # Fatal error in Process line__332 at C:/modeltech_10.0c/examples/composant-scrambler.vhd line 341 it joined my vhdl program thanks
Guest
#3240402
The error means exactly this: entity / package wrote: > Array lengths do not match. Left is 30 (29 > downto 0). Right is 14 (13 downto 0)
Guest
#3240404
That's easy: Your signal s is 30 bits wide and you try to assign a value to it which has only 14 bits. That's the problem. The error occurs in line 341. Cheers Marius ReplyPlease log in before posting. |