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Misunderstood in Verilog basics?
von Lapo (Company: Radioteknos) (lapo)

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Hi,
I'm quite new to Verilog but I've some code working but from time to 
time I got some uncompresible behaviour and I think I lake some knoledge 
in Verilog.

Here is a quick example of a more complex project, it works with div2 
module (/* go */) and don't with div5 module (/* no go */). Go / no go 
means I got ssoc signal on LED2 debug output or not.

1
module test_div_1(

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       /* iCEstick clk (12MHz) */

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       input  clkin,

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       /* 10MHz ref_in */

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       input  ref_in,

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       /* iCEstick leds */

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       output LED_GREEN, 

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       output LED0, output LED1, output LED2, output LED3,

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          /* ADC (DIV) spi */

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       );   

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15
   

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   SB_PLL40_CORE #(

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       .FEEDBACK_PATH("SIMPLE"),

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       /* $ icepll -i 12 -o 30 */

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       /* clkin=12MHz */

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       .DIVR(0),    /* DIVR =  0  (div 1) */

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       .DIVF(79),      /* DIVF = 79 (x80) */

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       .DIVQ(5),    /* DIVQ =  5 (div 6) */

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       /* main_clk=30MHz */

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       .FILTER_RANGE(3'b001)  /* FILTER_RANGE = 1 */

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       ) uut (

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        .LOCK(LED_GREEN),

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        .RESETB(1'b1),

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        .BYPASS(1'b0),

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        .REFERENCECLK(clkin),

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        .PLLOUTCORE(main_clk)

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        );

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   wire      main_clk;

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   wire      ref_in;

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   wire            soc;         

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   reg        ssoc;

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   wire       spi_m_clk;

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   /* soc generator (125kHz) */

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   div80 d80_1(ref_in, soc);

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   /* cs and clk generation */

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/* -----\/----- EXCLUDED -----\/-----

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   div2 div_spi_clk(ref_in, spi_m_clk); /-* go *-/

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 -----/\----- EXCLUDED -----/\----- */

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   div5 div_spi_clk(ref_in, spi_m_clk); /* no go */

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   always @ (negedge spi_m_clk)

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     ssoc<=soc;

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   /* TODO: remove (debug) */

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   assign LED0=spi_m_clk;

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   assign LED1=soc;

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   assign LED2=ssoc;

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   assign LED3=1'b0;   

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endmodule /* # test_div_1 end # */

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module div80(input in,

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        output out);

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   wire        in;

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   reg          out;

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   reg [6:0]        c;

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   initial

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     begin

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  c=7'b0000000;

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     end

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   always@(posedge in)

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     begin

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  if(c>=79)

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    begin

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       c<=0;

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       out<=1'b1;

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    end

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  else

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    begin

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       out<=1'b0;

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       c<=c+1;

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    end

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     end

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endmodule /* # div80 end # */

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module div5(input in,

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        output out);

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   wire        in;

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   reg         out;

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   reg [2:0]        c;

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   initial

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     begin

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  c=3'b000;

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     end

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   always@(posedge in)

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     begin

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  if(c>=4)

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    begin

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       c<=0;

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       out<=1'b1;

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    end

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  else

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    begin

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       out<=1'b0;

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       c<=c+1;

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    end

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     end

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endmodule /* # div5 end # */

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module div2(input in,

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      output out);

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   wire            in, out;

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   reg             c;

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   always@(posedge in)

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     begin

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  c<=!c;

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     end

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   assign out=c;

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endmodule /* # div2 end # */



div80 module output works fine...

Am I wrong in something about wire/reg? Or what ever?

If it matter I'm using ice40stick and icestorm toolchain (yosys, nextpnr 
and icepack).

Could you help me?
Thanks!

Lapo

  


  




  

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    Re: Misunderstood in Verilog basics?
  


  

    

      von
      
        Rick D.
        (rickdangerus)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Lapo wrote:
> Go / no go
> means I got ssoc signal on LED2 debug output or not.
LED debugging may work with microcontrollers, but not with FPGA.
Learn to use a simulator for debugging your designs.

  


  




  

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    Re: Misunderstood in Verilog basics?
  


  

    

      von
      
        Lapo
            (Company: Radioteknos)
        (lapo)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Rick D. wrote:
> LED debugging may work with microcontrollers, but not with FPGA.
> Learn to use a simulator for debugging your designs.

You are right. I should learn to use simulator and debugger in a lot
of situation.
In any case, the code was working but my logic design was wrong.

Thank you!

Lapo

  


  




  

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