I have a simple program. I am trying to input the counter output into a
memory address register and output the data that is in the memory
address register.
Memory Address Register Code:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 |
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4 | entity mar is
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5 | port(
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6 | mar_clk, mar_clr, mar_en : in std_logic;
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7 | mar_datain : in std_logic_vector(3 downto 0);
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8 | mar_dataout : out std_logic_vector(3 downto 0)
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9 | );
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10 | end entity;
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11 |
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12 | architecture behavioral of mar is
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13 | begin
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14 | process(mar_clk, mar_clr, mar_en, mar_datain)
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15 | begin
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16 | if(mar_clr = '1') then
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17 | mar_dataout <= (others => '0');
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18 | elsif(mar_clk'event and mar_clk = '1') then
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19 | if(mar_en = '0') then
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20 | mar_dataout <= mar_datain;
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21 | end if;
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22 | end if;
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23 | end process;
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24 | end behavioral;
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Buffer4 Code:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 |
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4 | entity buffer4 is
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5 | port(
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6 | buff4_en : in std_logic;
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7 | datain : in std_logic_vector( 3 downto 0 );
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8 | dataout : out std_logic_vector( 3 downto 0 )
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9 | );
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10 | end entity;
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11 |
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12 | architecture behavioral of buffer4 is
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13 | begin
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14 | process(buff4_en, datain)
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15 | begin
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16 | if(buff4_en = '1') then
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17 | dataout <= datain;
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18 | else
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19 | dataout <= (others => 'Z');
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20 | end if;
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21 | end process;
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22 | end behavioral;
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Program Counter Code:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_unsigned.all;
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4 |
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5 | entity pc is
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6 | port(
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7 | pc_ld, pc_en, pc_clk, pc_rst : in std_logic;
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8 | pc_datain : in std_logic_vector(3 downto 0);
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9 | pc_dataout : out std_logic_vector(3 downto 0)
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10 | );
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11 | end entity;
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12 |
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13 | architecture behave of pc is
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14 | signal count : std_logic_vector(3 downto 0) := "0001";
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15 | signal temp : integer;
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16 | begin
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17 | process(pc_clk, pc_rst)
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18 | begin
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19 | if(pc_rst = '1') then
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20 | count <= (others => '0');
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21 | elsif(pc_clk'event and pc_clk = '1') then
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22 | if(pc_ld = '1') then
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23 | count <= pc_datain;
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24 | elsif(pc_en = '1') then
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25 | count <= count;
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26 | temp <= conv_integer(count);
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27 | if(temp = 16) then
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28 | count <= (others => '0');
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29 | end if;
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30 | count <= count + 1;
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31 | end if;
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32 | end if;
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33 | end process;
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34 | pc_dataout <= count;
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35 | end behave;
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Test Code:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 |
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4 | entity test is
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5 | end entity;
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6 |
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7 | architecture behave of test is
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8 |
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9 | component mar
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10 | port(
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11 | mar_clk, mar_clr, mar_en : in std_logic;
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12 | mar_datain : in std_logic_vector( 3 downto 0 );
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13 | mar_dataout : out std_logic_vector( 3 downto 0 )
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14 | );
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15 | end component;
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16 |
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17 | component pc
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18 | port(
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19 | pc_ld, pc_en, pc_clk, pc_rst : in std_logic;
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20 | pc_datain : in std_logic_vector(3 downto 0);
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21 | pc_dataout : out std_logic_vector(3 downto 0)
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22 | );
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23 | end component;
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24 |
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25 | component buffer4
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26 | port(
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27 | buff4_en : in std_logic;
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28 | datain : in std_logic_vector( 3 downto 0 );
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29 | dataout : out std_logic_vector( 3 downto 0 )
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30 | );
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31 | end component;
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32 |
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33 | signal databus : std_logic_vector(7 downto 0);
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34 | signal addressbus : std_logic_vector(3 downto 0);
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35 |
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36 | signal gclk : std_logic;
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37 | signal mar_clr, mar_en : std_logic;
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38 | signal pc_ld, pc_en, pc_rst : std_logic;
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39 |
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40 | signal buff4_en : std_logic;
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41 | signal dataout : std_logic_vector(3 downto 0);
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42 |
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43 | signal mar_datain, mar_dataout : std_logic_vector(3 downto 0);
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44 | signal pc_dataout : std_logic_vector(3 downto 0);
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45 |
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46 | begin
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47 | U1 : pc port map(pc_ld, pc_en, gclk, pc_rst, databus(3 downto 0), pc_dataout);
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48 | U2 : buffer4 port map(buff4_en, pc_dataout, databus(3 downto 0));
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49 | U3 : mar port map(gclk, mar_clr, mar_en, databus(3 downto 0), addressbus);
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50 |
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51 | stim_process : process
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52 | begin
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53 | gclk <= '0';
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54 | wait for 10 ns;
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55 | pc_ld <= '0';
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56 | pc_en <= '1';
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57 | pc_rst <= '0';
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58 | buff4_en <= '1';
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59 | mar_clr <= '0';
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60 | mar_en <= '0';
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61 | gclk <= '1';
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62 | wait for 10 ns;
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63 |
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64 | gclk <= '0';
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65 | wait for 10 ns;
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66 |
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67 | assert false report "Reached end of test. Start GTKWave";
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68 | wait;
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69 | end process;
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70 | end behave;
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I have attached the simulation of the test.vhdl. The Memory Address
Registers takes the input and doesn't output it on the address bus. How
can I make the Memory Address Register output the data on the address
bus?