library ieee;
use ieee.std_logic_1164.all;

entity test is
end entity;

architecture behave of test is

component mar
	port
	(
		mar_clk                        : in    std_logic;
		mar_clr                        : in    std_logic;
		mar_en                         : in    std_logic;
		mar_datain                     : in    std_logic_vector(3 downto 0);
		mar_dataout                    : out   std_logic_vector(3 downto 0)
	);
end component;

component pc
    port
	(
        pc_ld                          : in    std_logic;
		pc_en                          : in    std_logic;
		pc_clk                         : in    std_logic;
		pc_rst                         : in    std_logic;
        pc_datain                      : in    std_logic_vector(3 downto 0);
        pc_dataout                     : out   std_logic_vector(3 downto 0)
    );
end component;

component buffer4
	port
	(
		buff4_en                       : in    std_logic;
		datain                         : in    std_logic_vector(3 downto 0);
		dataout                        : out   std_logic_vector(3 downto 0)
	);
end component;

signal databus                         : std_logic_vector(7 downto 0) := (others => '0');
signal addressbus                      : std_logic_vector(3 downto 0) := (others => '0');
signal gclk                            : std_logic := '0';
signal mar_clr                         : std_logic := '0';
signal mar_en                          : std_logic := '0';
signal pc_ld                           : std_logic := '0';
signal pc_en                           : std_logic := '0';
signal pc_rst                          : std_logic := '0';
signal buff4_en                        : std_logic := '0';
signal pc_dataout                      : std_logic_vector(3 downto 0) := (others => '0');

begin

    U1 : pc
	port map
	(
        pc_ld                          => pc_ld,
		pc_en                          => pc_en,
		pc_clk                         => gclk,
		pc_rst                         => pc_rst,
        pc_datain                      => databus(3 downto 0),
        pc_dataout                     => pc_dataout
    );

    U2 : buffer4
	port map
	(
		buff4_en                       => buff4_en,
		datain                         => pc_dataout,
		dataout                        => databus(3 downto 0)
	);

    U3 : mar
	port map
	(
		mar_clk                        => gclk,
		mar_clr                        => mar_clr,
		mar_en                         => mar_en,
		mar_datain                     => databus(3 downto 0),
		mar_dataout                    => addressbus
	);

	gclk <= not gclk after 5 ns;

    stim_process : process
    begin
        wait for 10 ns;
        pc_ld <= '0';
        pc_en <= '1';
        pc_rst <= '0';
        buff4_en <= '1';
        mar_clr <= '0';
        mar_en <= '0';
        wait;
    end process;

end behave;