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Forum: FPGA, VHDL & Verilog Converting binary number to seven-segment-display


Converting binary number to seven-segment-display
von Eric J. (coderic)

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My goal is to convert a binary input number to a std_logic_vector 
signaling which segments to activate/deactivate on a 
seven-segment-display.
'segments' is basically a vector, with each bit representing a segment a 
through g, with the display being enumerated clockwise from the top (a) 
to the upper left (f). The middle segment is g.

When I run this, I get an error at each if line, telling me that the 
'then's are wrong and that I should properly use a 'generate' - which is 
not really what I am trying to do.
Can someone tell me how to fix this?

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library ieee;

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use ieee.std_logic_1164.all;

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entity BCDDecoder is

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port (

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    digit : in std_logic_vector(3 downto 0);

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    segments : out std_logic_vector(6 downto 0)

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);

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end BCDDecoder;

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architecture rtl of BCDDecoder is

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begin

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if digit = "0000" then

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    segments <= "1111110";

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end if;

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if digit = "0001" then

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    segments <= "0110000";

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end if;

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if digit = "0010" then

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    segments <= "1101101";

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end if;

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if digit = "0011" then

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    segments <= "1111001";

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end if;

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if digit = "0100" then

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    segments <= "0110011";

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end if;

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if digit = "0101" then

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    segments <= "1011011";

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end if;

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if digit = "0110" then

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    segments <= "0011111";

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end if;

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if digit = "0111" then

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    segments <= "1110000";

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end if;

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if digit = "1000" then

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    segments <= "1111111";

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end if;

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if digit = "1001" then

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    segments <= "1110011";

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end if;

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end architecture rtl;


  


  




  

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    Re: Converting binary number to seven-segment-display
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Eric J. wrote:
> When I run this, I get an error at each if line
You can use if-then only inside a process. As a concurrent statement use 
when-else or with-select:
https://insights.sigasi.com/tech/signal-assignments-vhdl-withselect-whenelse-and-case/

  


  




  

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