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Forum: FPGA, VHDL & Verilog Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving


Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving
von Omar K. (Company: Middle East University) (omar17)

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** Write the MCU super-loop version (state-machine with fixed heartbeat) 
of the following code:
1
while(1) {

2
   wt(2);

3
   AA();

4
   wt(6);

5
   BB();

6
   wt(4);

7
   CC();

8
}


**Then, Consider above question. Replace:

AA() with aa = bb + cc;
BB() with bb = aa * cc;
CC() with cc = bb - aa;

and write the corresponding Verilog RTL.

: Edited by Moderator
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Re: Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Omar K. wrote:
> wt(2);
What means that? Is it a delay like "wait for 2 clocks"?

> and write the corresponding Verilog RTL.
As a VHDL guy I would search the internet how a FSM is coded in Verilog. 
The search would not last long as this is a very basic thing. Then one 
counter for the delay. Thats all folks.


So start with something, then ask a particular question when you 
encounter specific problems. But it won't work here to wait for someone 
doing your homework.

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