Attached ModelSim VHDL design of System Reset by PLL Locked Signal. Regards Alex.
Attached files:
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Reset.PNG
53 KB
Alexander S. wrote: > System Reset by PLL Locked Signal You need 99 kByte attachment for a system reset? SRSLY?
Duke Scarring wrote: > Alexander S. wrote: >> System Reset by PLL Locked Signal > You need 99 kByte attachment for a system reset? SRSLY? It's not size of file for load to the FPGA RAM, it's text of design with comments inside with Model Sim simulation project. Regards Alex.
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Edited by User
Modelsim simulation project? I do a very lot of simulations, but never needed a modelsim project for that. To start modelsim you need only a couple of commands:
1 | vlib work |
2 | vcom *.vhd |
3 | vsim toplevel_of_testbench -gui |
Inside modelsim the same:
1 | add wave * |
2 | run -all |
Please, please, please: Stop wasting bandwidth with your zip files! Duke
Duke Scarring wrote: > Modelsim simulation project? > I do a very lot of simulations Not only you participate in this forum. There are designers who do not have a simulation experience like you, or do it for the first time in their life. Regards Alex.
-gb- wrote: > Or not locked. And I make reset synchronous with delay. It's problem. Regards Alex.
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Edited by User
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