Hi,
I am new to HDL language. I have written and compile basic Counter
Verilog code. But i need store 32 bit counter values as 4 8-bit
registers ? Please someone help me
module counter
#(parameter WIDTH=8)
(
input clk, enable, rst_n,
output reg [WIDTH-1:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule
Saraswathy S. wrote:> 32 bit counter
There is no 32 bit counter in that design.
> But i need store 32 bit counter values as 4 8-bit registers ?
Where do you need to store the counter? Whats your actual problem? Whats
the original text of your exercise?
Define a local 32bit counter register and connect your Data_out_x to the
corresponding bytes of this register. Use 'logic' or 'wire' instead of
'reg' type for the outputs.
Make the 32bit counter as in your first post, and then assign the right
portion of the counter to the output byte 0..3. Here the second byte,
the others are up to you:
1
...
2
assignData_out_1=count[15:8];
3
...
You don't need to declare the count reg as output, just make it a local
register.
I started verilog two weeks ago, so my example may not be the best.
Actually, if it is wrong or could be improved, PLEASE suggest.
The code is modified to emphasize the fact that it does what you need.
The counter is not starting at 0, nor is it reset, but that is on
purpose. Read the comments and change whatever you need.
This is what I would do:
Saraswathy S. wrote:> Please check now whether my code is right.
Not quite. The Synthesis tool will give you a few errors.
You need to declare all input and output ports inside the first
parenthesis section.
You also have the Data_out_0..3 as output ports, so they have to go
there.
If you don't need to access the count from outside the module, declare
it after the parenthesis as follows:
1
modulecounter
2
(
3
...// in-out ports here
4
);
5
reg[31:0]count;// a register used only inside the module