Hello, from the  theory in the attached photo i have implemented  the 
formula  in the VERILOG code bellow, the syntax check was fine but when 
i tried in XILINX  to force values  the simulation gives me an empty 
screen and says:

# run 1.00us
INFO: Simulator is stopped.

where did i go wrong in entering the coefficients?
Thanks

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module vvco(fo,vctl,kv);

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input fo,vctl,kv;

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reg vco_b=1'b0;

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reg fo_b=3'b0;

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reg vctl_b=3'b0;

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reg kv_b=3'b0;

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always #((1/fo_b-vctl_b*kv_b/fo_b^2)/2) vco_b<=~vco_b;

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endmodule