EmbDev.net

Forum: FPGA, VHDL & Verilog Creating Multi Files

von Christin K. (christinkimeri)

2017-02-20 19:42

Rate this post

•	▲ useful ▼ not useful

Im exporting the data to a  file using print but now I need to solve 
this system for different values of my parameters and i dont want to 
create different files manually. Does anyone knows how can I create 
different files to store the different solutions i get for the different 
values of my parameters?

Sorry for my english and thanks!

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote

Re: Creating Multi Files

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-02-20 22:42

Rate this post

•	▲ useful ▼ not useful

Christin K. wrote:
> Im exporting the data to a  file using print
From WHERE?

> Does anyone knows how can I create different files
With WHAT?
What language do you use?

2017-02-20 22:42: Edited by Moderator

Report post Edit Delete Quote selected text Reply Reply with quote

Re: Creating Multi Files

von Christin K. (christinkimeri)

2017-02-20 23:19

Rate this post

•	▲ useful ▼ not useful

I am using VHDL language.

Different data should be write into  different files by creating 
manually...

Below is the equivalent C code. I am not able convert it to VHDL..

FILE *files[numfiles];
for (int i = 0; i < numfiles; i++)
{
    char filename[20];
    sprintf(filename, "results%d.dat", i);
    files[i] = fopen(filename, "w");
}

Report post Edit Delete Quote selected text Reply Reply with quote

Re: Creating Multi Files

von Duke Scarring (Guest)

2017-02-21 09:01

Rate this post

•	▲ useful ▼ not useful

Here is a starting point:

entity multiple_files_tb is
end entity multiple_files_tb;
library std;
use std.textio.all;
architecture testbench of multiple_files_tb is
    constant filename : string := "results";
    main: process
        file        outfile : text;
        variable    status  : file_open_status;
        variable    l       : line;
    begin
        for index in 0 to 20000 loop
            file_open( status,  outfile, filename & integer'image( index) & ".dat", write_mode);
            if status = open_ok then
                write( l, "this is file nr. " & integer'image( index));
                writeline( outfile, l);
            else
                report "error opening file " & integer'image( index);
            end if;
            file_close( outfile);
        end loop;
        wait; -- forever
    end process;
end architecture testbench;


Text and file processing is no fun in VHDL. I would write everything 
with a tag in a single file.
After that you could any better tool for processing like python, matlab, 
c, you-name-it.

Duke

Report post Edit Delete Quote selected text Reply Reply with quote

Re: Creating Multi Files

von Christin K. (christinkimeri)

2017-02-22 05:07

Rate this post

•	▲ useful ▼ not useful

Thanks a lot Duke Scarring.

       Requirement is in VHDL.Can you suggest where can i get materials 
on File system in VHDL.

Report post Edit Delete Quote selected text Reply Reply with quote

Re: Creating Multi Files

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-02-22 07:53

Rate this post

•	▲ useful ▼ not useful

Christin K. wrote:
> Can you suggest where can i get materials on File system in VHDL.
Look there somewhere around page 500:
http://xilinx.eetrend.com/files-eetrend-xilinx/forum/201404/7000-11806-the_designers_guide_to_vhdlpeter_j.ashenden.pdf

And there was stefanvhdl.org ...
As a pity its offline now, but with wayback you ca look a captured 
version of the page:
https://web.archive.org/web/20160914062538/http://stefanvhdl.com/vhdl/html/index.html

2017-02-22 07:54: Edited by Moderator

Report post Edit Delete Quote selected text Reply Reply with quote

Re: Creating Multi Files

von Christin K. (christinkimeri)

2017-02-22 19:40

Rate this post