EmbDev.net

Forum: FPGA, VHDL & Verilog reduce procedure/function parameter list


Author: bumo (Guest)
Posted on:

Rate this post
0 useful
not useful
I am currently working on a testbench which consists of several 
procedures.
The problem i am facing is that, even for small blocks embedded in 
procedures, the number of parameters is very high if i have to loop them 
back.
This makes the procedure parameter list very complicated to read/write 
and even worse, the code harder to understand.

eg (useless, but shows the problem)

  procedure foo (
    signal clk        : in  std_logic;
    signal a0         : in  std_logic; -- loop signal in
    signal a1         : in  std_logic;
    signal b0         : out std_logic; -- loop signal out
    signal b1         : out std_logic) is
  begin
    wait until rising_edge(clk);
    b0 <= a0;
    b1 <= a1;
    wait until rising_edge(clk);
    b0 <= '0';
    b1 <= '0';
  end procedure foo;

Is there a way to bypass this problem, eg by accessing signals from from 
the testbench begin section from within the procedure? (I am aware of 
the fact that this would lead to unportable code...)

Thank you in advance.

Author: bumo (Guest)
Posted on:

Rate this post
0 useful
not useful
Although I had to change a lot, I ended up using a record.

Author: VHDL hotline (Guest)
Posted on:

Rate this post
0 useful
not useful
Have you tried using "inout" for the same signal instead of separate in 
and out?

Author: bumo (Guest)
Posted on:

Rate this post
0 useful
not useful
The signals are from different sources, therefore inout is no option.
However, I had to use inout for the record, since signals are 
read/written.

I figured that this also leads to subtile problems. Since the record is 
used with inout, it does not seem to be possible to write to a signal 
within the record from a different process, even if it is only written 
in a single process?!

Author: daniel__m (Guest)
Posted on:

Rate this post
0 useful
not useful
hi,

maybe "impure" can help you.

also maybe it is helpful declaring the procedures/functions within the 
process, which uses them.

Author: bumo (Guest)
Posted on:

Rate this post
0 useful
not useful
daniel__m wrote:
> hi,
>
> maybe "impure" can help you.
>
> also maybe it is helpful declaring the procedures/functions within the
> process, which uses them.

thanks, i was not aware of the "impure" keyword.

Very strange, when the signal within the record, which is shown as 
multiple driven in the simulator is initialized with high impedance, 
everything works fine...

Author: Duke Scarring (Guest)
Posted on:

Rate this post
0 useful
not useful
bumo wrote:
> Very strange, when the signal within the record, which is shown as
> multiple driven in the simulator is initialized with high impedance,
> everything works fine...

I think there where some inprecise formulations in the VHDL standard a 
while around.
In my modelsim.ini I find the following section:
; Determine how mode OUT subprogram parameters of type array and record are treated.
; If 0 (the default), then only VHDL 2008 will do this initialization.
; If 1, always initialize the mode OUT parameter to its default value.
; If 2, do not initialize the mode OUT out parameter.
; Note that prior to release 10.1, all language versions did not initialize mode
; OUT array and record type parameters, unless overridden here via this mechanism.
; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
; initialization, unless overridden here.
; InitOutCompositeParam = 0
You also have to check how your synthesizer works on that point.

Duke

Author: bumo (Guest)
Posted on:

Rate this post
0 useful
not useful
> I think there where some inprecise formulations in the VHDL standard a
> while around.
>
> Duke

Thanks for pointing that out, I will have a look.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig