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Forum: FPGA, VHDL & Verilog VHDL multiplier block


Author: Esteban (Guest)
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Hi!

I've been trying to do a 16 bit multiplier block using vhdl:

------------------------------------------------------------------------ 
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Multiplier is
  port(
  x,B: in std_logic_vector(15 downto 0);
  R: out std_logic_vector(15 downto 0)
  );
end Multiplier;

architecture Behavioral of Multiplier is
signal s32_R: std_logic_vector(31 downto 0);

begin

  Multiplication: process(x,B)
  begin
    s32_R <= std_logic_vector(signed(x)*signed(B));
    R <= s32_R(15 downto 0);
  end process Multiplication;

end Behavioral;
------------------------------------------------------------------------ 
---

When the simulation is done the result is at the first 16 bits of the 32 
bits value at s32_R signal but it does not move to the output port 
labeled R, instead of the desire result, port R keep the unitialized 
value 'UUUUUUUUUUUUUUUU'.

Is it wrong to use "R <= s32_R(15 downto 0);"? Is it a better or 
correctly way to describe this operation? It's just moving the 16 less 
significant bits of the s32_R signal into the entity output R.

Thanks for reading! :)

Author: daniel__m (Guest)
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hi,

a classical one:

Esteban wrote:
> Multiplication: process(x,B)

sensitive list incomplete

Author: Hosenmatz (Guest)
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This seems, I guess, to be an issue regarding the verification process.

How exactly did you do it? How long was the simulation? How long was it 
in relation to the time, the multiplier takes? How long keeps R the 
uninitialized state?

The main point is, that you possibly forgot, that you describe 
structures rather than writing programs. While the multiplication is 
done, the second line, assigning (or better say transportation) of s32_R 
to R is at and during the very same time in effect, - or say: parallel 
to -, the multiplication.

So, if you stop simulation when the multiplication is done, the transfer 
to R had just begun, not finished, as you may assume.

Whether that assumption matters, depends in turn on whether you 
simulated a real design or not. It is, additionally, true, that such a 
simple "put-through" or say "and identity" in terms of math, is 
optimized away in a synthesized design.

So I assume, that you showed us a simplified process, whose real 
version, make use of the intermediate result s32_R, so that it wasn't 
optimized away, and shows that "delayed" behavior, which you don't 
recognize because you stopped the simulation too early.

Author: berndl (Guest)
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Esteban wrote:
--Multiplication: process(x,B)
--  begin
    s32_R <= std_logic_vector(signed(x)*signed(B));
    R <= s32_R(15 downto 0);
--  end process Multiplication;

Author: P. K. (pek)
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Sensitivity list seems incomplete to me. Maybe it works after adding 
s32_R to it.

Author: js (Guest)
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Instead of adding s32_R to the sensitivity list I suggest to use a 
variable.
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Multiplier is
  port(
  x,B: in std_logic_vector(15 downto 0);
  R: out std_logic_vector(15 downto 0)
  );
end Multiplier;

architecture Behavioral of Multiplier is
begin
  Multiplication: process(x,B)
    variable s32_R: std_logic_vector(31 downto 0);
  begin
    s32_R := std_logic_vector(signed(x)*signed(B));
    R <= s32_R(15 downto 0);
  end process Multiplication;
end Behavioral;
---

Author: Van Loi Le (Guest)
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You can see a project over multiplication of matrixs here using VHDL:
http://fpga4student.blogspot.sg/2016/11/matrix-mul...

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