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Forum: FPGA, VHDL & Verilog Implementation error due to UCF FILE (MOJO)


Author: George Saman (Company: nonne) (georgesaman)
Posted on:

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I get it this error when i generate bin file, I am using Xilinx ISE and 
it shows that the synthesize part is done. I am new to VHDL and FPGA 
development.




---------*--**-*-*-*-*-*-*-*-*-*-*--*-*-*-*-*--*-*-*-*-*-*-*-**-*-*-*-
Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:59 - Constraint <NET "led<6>" LOC = P124 ;>
   [D:/MOJO/verilog/mojo-base-project-master/mojo-base-project-master/src/m 
ojo.u
   cf(12)]: NET "led<6>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

WARNING:ConstraintSystem - A target design object for the Locate 
constraint
   '<NET "led<6>" LOC = P124 ;>
   [D:/MOJO/verilog/mojo-base-project-master/mojo-base-project-master/src/m 
ojo.u
   cf(12)]' could not be found and so the Locate constraint will be 
removed.

ERROR:ConstraintSystem:59 - Constraint <NET "led<7>" LOC = P123 ;>
   [D:/MOJO/verilog/mojo-base-project-master/mojo-base-project-master/src/m 
ojo.u
   cf(13)]: NET "led<7>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

WARNING:ConstraintSystem - A target design object for the Locate 
constraint
   '<NET "led<7>" LOC = P123 ;>
   [D:/MOJO/verilog/mojo-base-project-master/mojo-base-project-master/src/m 
ojo.u
   cf(13)]' could not be found and so the Locate constraint will be 
removed.

Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     2
  Number of warnings:   2

Total memory usage is 192172 kilobytes

Total REAL time to NGDBUILD completion:  21 sec
Total CPU time to NGDBUILD completion:   21 sec

One or more errors were found during NGDBUILD.  No NGD file will be 
written.

Writing NGDBUILD log file "gates2_top.bld"...

Author: Duke Scarring (Guest)
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George S. wrote:
> ERROR:ConstraintSystem:59 - Constraint <NET "led<6>" LOC = P124 ;>
>    [D:/MOJO/verilog/mojo-base-project-master/mojo-base-project-master/src/m
> ojo.u
>    cf(12)]: NET "led<6>" not found.  Please verify that:
>    1. The specified design element actually exists in the original
> design.
>    2. The specified object is spelled correctly in the constraint source
> file.

You need to set a signal to outputs led<6> and led<7> in your code:
module ...
...
...

led[6] <= '1';
led[7] <= '0';

endmodule
If you have no signal assignment than the signal will be optimized away.

Duke

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