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Forum: FPGA, VHDL & Verilog Basic Question


Author: Elena Cososchi (Company: TU Darmstadt) (elena_coso)
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Hi all,

I am newly working with Cosmos OpenSSD, a real SSD Board that deploys 
the flash Storage Controller and the Error Correction Code on FPGA. The 
Software is C++, yet the firmware is VERILOG. It is my first time 
working with Verilog and for now I only want a small trick in order to 
test a hypothesis.

My question is:

Let's say I have
assign nxt_parity[i] = cur_parity[i-1];

I want nxt_parity vector to have only 1s, independent of cur_parity. Can 
I do this trick in the assign?
parameter PARITY_ONE = 1;
assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE));

Thank you very much for any hint you may provide!

best,
Elena

Author: Lothar Miller (lkmiller) (Moderator)
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Elena C. wrote:
> I want nxt_parity vector to have only 1s, independent of cur_parity.
So why do you need cur_parity at all?

Author: Elena Cososchi (Company: TU Darmstadt) (elena_coso)
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Hi,

because we will do some time measurement ans simulate the real encoding 
process.

So my concern is: can I do this in the assign statement?

thanks!
Elena

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