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Forum: FPGA, VHDL & Verilog Timing Requirements - Worst case Removal Slack


Author: Bryan (Guest)
Posted on:

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Hallo all,

I have a critical warning of Worstcase removal slack of -2.461.

From node: - altera_reserved_tck
To node:   pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967

I am not sure if I should ignore this warning as the path is the open 
core plus logic and it should constrain itself and since it operates on 
the slow JTAG clock

So the reason I see the failures is that the logic isn't constrained and 
not necessarily true failing paths. Unfortunately those are randomized 
names so you can't add in your own constrains easily. Since I use OCP, 
maybe it shows up as a failing path.

Any suggestions? Should I ignore it or fix it?

Thanks!

Author: Markus F. (mfro)
Posted on:

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Bryan wrote:
>
> Any suggestions? Should I ignore it or fix it?
>
> Thanks!

https://www.altera.com/support/support-resources/k...

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