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Forum: FPGA, VHDL & Verilog UART with Adder


Author: Maxim Moor (max_min)
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Hi,
i need to interface the UART implemented in VHDL, with a full adder ,
to take the output of the uart and add it to the input of the UART
any help please?

Author: user (Guest)
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is this your homework?

Author: Maxim Moor (max_min)
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No this my grandma homework

Author: Falk (Guest)
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Beware of the death adder!

https://en.wikipedia.org/wiki/Death_adder

;-)

Author: Lothar Miller (lkmiller) (Moderator)
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Maxim M. wrote:
> Hi, i need to interface the UART implemented in VHDL
What UART?

> with a full adder
Of course. In VHDL a '+' operator results in a full (featured) adder. So 
thats the most simple part of your grannys homework.

> to take the output of the uart and add it to the input of the UART
????

> any help please?
Of course. But first YOU show something that your granny wrote, then WE 
can discuss about. No one here wants to do your grannys homework on his 
own...

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