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Forum: FPGA, VHDL & Verilog Generation of gating signals using VHDL and FPGA


Author: Nirav Bhatt (Company: Uvic) (nirav_bhatt)
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I have a code to generate gating signals and need help to have a dead 
gap in between the two output signals G1 and G2 of 200 nanoseconds 
through out the operation period.
When i say dead gap there should be no output at that time not in G1 nor 
in G2.
Picture 1 (attached) shows the exact need of the operation.
Code is attached for reference.

Author: Lothar Miller (lkmiller) (Moderator)
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Two things first:
1. jpeg ist NOT an adequate format for screenshots.
Use png instead (have a look at the artifacts around the letters).
2. a screenshot ist not an adequate format for a VHDL code file.
Use a *.vhd text file instead (its much easier to copy&paste something).

Nirav B. wrote:
> and need help to have a dead gap in between the two output signals G1
> and G2 of 200 nanoseconds through out the operation period.
You are lucky: 200ns are 10*20ns, and 20ns is your clock. But: i cannot 
find that value in the sketch. There the dead gap is 10ns... :-o
Why are there several signal changes on the rising and several on the 
falling edge?
I cannot find the signals (start*) from the sketch in the code.

Why that "phases"-loop inside this module. I would write one PWM and 
instatiante it "phases" times in the upper-level module. In that case 
you only have to proof that this single PWM is running fine.
In your case you will never be able to test the whole range of 
possibilities (becuase there is no range, even a negative number of 
"phases" is allowed as generic...).

All in all it should be fairly easy here: you simply need to crate the 
PWM. After having that you generate the dead time between the outputs.

I'm doing the dead time generation for a H-bridge that way:
http://www.lothar-miller.de/s9y/archives/58-Totzei...

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