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Forum: FPGA, VHDL & Verilog [HELPME] How to unstuck at VCC?


Author: Paulo Henrique Silva (Guest)
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I need to make an output pulse (within certain conditions) becomes a '1' 
constant (in an LED).
I was able to code, but the output is stuck at VCC. I do not know how to 
fix this. Can anyone help me please?

Code:


ARCHITECTURE behavioral OF  check_minutes IS
  SIGNAL aux: STD_LOGIC := '0';
BEGIN
  accept_minutes: PROCESS(enable,data) --processo de aceitar ou não a 
temperatura inserida.
  BEGIN
          IF(data>="000001" AND data<="111011" AND enable='1') THEN
           aux <= '1';
          END IF;
  END PROCESS accept_minutes;
  minled <= aux;
END ARCHITECTURE behavioral;

Author: Pat a Mat (Guest)
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You have to set "aux <= '0' in an else-tree. This one generates a latch.

Author: Paulo Henrique Silva (Guest)
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thank u for ur reply, pat. It really works, but I want to make a 
CONSTANT '1'. Can u help me with that? what u say generates one pulse. I 
want one constant 1 after this pulse.

Author: Pat a Mat (Guest)
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> I want one constant 1 after this pulse.

In this case you need a condition to reset 'aux' to '0' at the time you 
want. For example when 'enable = 0' or any other signal.

By the way: Such combinatorical logic generates latches! Only for 
simulation is it ok, but in real hardware is it very problematic. The 
better way is to use a register. But this needs a proces with a clock.

Author: Paulo Henrique Silva (Guest)
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I'm sending prints of cases, both code and simulation. It's in attach.

In second case the constant 1 works, but before the constant 1, it's 
unknown, as u can see. do u know how do I transform this unknown to '0'?

Author: Achim S. (Guest)
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Paulo Henrique Silva wrote:
> In second case the constant 1 works, but before the constant 1, it's
> unknown, as u can see. do u know how do I transform this unknown to '0'?

Your shown code describes how you assign the signal "aux". It has an 
initialization to zero. If your simulator takes the init-value into 
account, aux should never be undefined. If your simulator ignores the 
init-value, then aux should at least be well defined once enable gets 
high.

But your simulation result does not show the signal "aux" but a signal 
"minled" which does not at all appear in your code. Maybe you show us, 
how minled depends on aux. There one should the answer to your question.

By the way: as you have a clock (according to your simulation) you 
really should follow the recommendation of Pat a Mat and work with 
registers instead of latches. That will give you much less trouble.

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