Robert wrote:
> Below is the code:
> entity Gen_150 is
A VHDL code start well before the keyword "entity"...


> b_out <= NOT tmp after 10ns; -- output delayed by 10ns
Thats not synthesizeable! You know that?


> I want to increase the duty cycle slowly from 0%-50%
Try that and change the value of pwm:

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signal count: integer:=0;

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signal pwm: integer:=100;

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:

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:

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elsif(sys_clk'event and sys_clk='1') then

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  count <=count+1;

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  if (count = 332) then

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     count <= 0;  

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  end if;

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end if;

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tmp <= '1' when (count < pwm) else '0';

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:

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:

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end process;

Now you have a changing output signal. And the only thing you must du, 
is to produce a ramp on the "pwm" signal. Thats fairly easy...

Robert wrote:
> And I am getting an syntax error for the below:
>
> tmp <= '1' when(count < pwm) else tmp <= '0';
Of course you do. What's the correct syntax for the when/else statement?
Why didn't you simply copy it from me?
Mine will not conclude in an error message.

And for the PWM value: let start it from 0. And then increment it every 
500000/166 clocks. So you will only need an additional counter from 0 to 
500000/166. And when the counter reaches that value you must reset it to 
0 and increment the PWM value until its 166.

You see that there's no whatsoever "case" statement necessary at all and 
the PWM value will increase smoothly from 0 to 166...

Robert wrote:
> Is it ok to add a min delay(is 10ns too much?)
Only you know that...

> just by adding a temp register to delay out_b?
With a 100MHz clock thats the only way to do it...

Wil wrote:
> How do I introduce a 180° phase shift between a_out and b_out.
> I tried using an inverting output.
A phase shift is only defined for sinusoidal signals. And then inverting 
is correct.

> How do I introduce a 180° phase shift between a_out and b_out.
What you want in fact is a delay of half the cycle duration for one of 
the signals.

Wil wrote:
> How do I give a synthesizable delay.
Use a second PWM unit that counts half a cycle delayed.
Or simply use a shift register.