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Forum: FPGA, VHDL & Verilog Example of using Dual Port Ram (Lattice MachXO2)?


Author: Kenny Millar (kennym)
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Hi

I'm using a Lattice MachXO2 and the Lattice Diamond design software.
In my design I want to feed data into a Pseudo Dual Port Ram from one 
module (A simple UART) and read it out from another (an LED controller).

Lattice provides a RAM_DP module using IPExpress which is implemented 
using the MachXO2's EBR Ram blocks.

I have no trouble generating and instantiating the RAM_DP module using 
IPExpress and I have read through "Memory Usage Guide for MachXO2 
Devices" on Lattice's website. It gives good info on how the instatiate 
the module, and the timing diagrams.

This is how the module is declared, once generated from IP Express:
 module pdpram (WrAddress, RdAddress, Data, WE, RdClock, RdClockEn, 
Reset, WrClock, WrClockEn, Q);

What I'm looking for is some help in actually using the module. As far 
as I can see the Read and Write clocks need to be out of phase, so I'm 
not sure how to go about that. Do I even need to worry about that?  (I'm 
pretty new to FPGA, but getting there!).

So, does anyone have any examples of how to use the Pseudo Dual Port Ram 
module?

Author: Lattice User (Guest)
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Kenny M. wrote:
> >
> What I'm looking for is some help in actually using the module. As far
> as I can see the Read and Write clocks need to be out of phase, so I'm
> not sure how to go about that. Do I even need to worry about that?

The clocks don't need out of phase, so nothing to worry about.

You need only take care in case of reading and writeing with the same 
address. In this case the data read may be invalid at higher clock 
speeds.

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