EmbDev.net

Forum: FPGA, VHDL & Verilog Ethernet MAC - PHY transmit


Author: Szymon Piotrowski (sion111)
Posted on:
Attached files:
  • TX.txt (7.42 KB, 184 downloads)

Rate this post
0 useful
not useful
Hello,
I am trying to write a simple template frame transmitter using MII in 
verilog. The ethernet frame format I am using looks like

preamble (7B) > frame delimeter (1B) > Dest. MAC (6B of 1's to 
broadcast) > Source MAC ( 00:11:22:33:44:55) > LENGTH (4B, typing 100 
for 100 octetcs of data) > DATA (100 octets of 0's) > FCS (4B, 
calculated using http://www.zorc.breitbandkatze.de/crc.html) with data 
(from dest MAC to the end of actual data) i've just provided.

I am aware of the fact of reverse order of bits needed by the ethenret 
frame. To capure any data from PHY i am using Wireshark, but it shows 
only some frames from the PC (used, for example, to establish connection 
or trying to communicate, i guess).

Is the timing of TXEN correct? Or is it something wrong with the 
implementation?
I would appreciate any help in making the code sending that frame.

(The files attached presents the code itself and the start and end of 
frame to be transmitted (to show the TXEN timing)

Author: Verilog hotline (Guest)
Posted on:

Rate this post
0 useful
not useful
What is your target platform for the Verilog code?
From what I read it sounds like you are trying to run Verilog code on 
your PC to send something through your PC network card.

Author: Szymon Piotrowski (sion111)
Posted on:

Rate this post
0 useful
not useful
The transmitter code is a part of a bigger project. It runs on a Lattice 
LFXP2 fpga. The FPGA is connected to MTXC (the clk of the module) MTXEN, 
MTXER and MTXD3-0 of PHY device (KSZ8863). PC network card is connected 
to the PHY device. I can see that the link is established to 100Mb/s 
(what is correct since the external crystal provides 25MHz). Wireshark 
does not show any packet from the PHY.

Author: Verilog hotline (Guest)
Posted on:

Rate this post
0 useful
not useful
Are you syncing the tx signals to the external clock?
Are you sure your CRC is correct?
Are you sure that your PHY really sends your packet?

Most PHYs have a loopback that can be enabled for debug. You could test 
if your PHY responds by enabling a loopback to PC side (and send sth. to 
the PHY, i.e. using Ostinato) and you can test if your PHY would really 
send your packet with the loopback to MAC side.

Author: Szymon Piotrowski (sion111)
Posted on:

Rate this post
0 useful
not useful
1. they are synced to the MTXC pin that is PHY transmit clok pin.
2. it can be as correct as the internet caclulator done it (but i have 
used MIIM to make a change in phy's control register to switch all 
packages, including bad ones).
3. no, i am not, since neither wireshark nor etherdetect shows anything.

The is only a TX side used for now, so a loopback may not come in handy.

Author: Dose (Guest)
Posted on:

Rate this post
1 useful
not useful
I have written also a MII interface in VHDL

see
 Beitrag "Ethernet GMII"

The starting code has a mistake in the preamble.

Author: Lattice User (Guest)
Posted on:

Rate this post
1 useful
not useful
Dose wrote:
> I have written also a MII interface in VHDL
>
> see
>  Beitrag "Ethernet GMII"
>
> The starting code has a mistake in the preamble.

That would Wireshark not prevent to see something.
But a fully functionally Wireshark requires a
network card which can be set to promiscous mode and
that also will forward packets with incorrect FCS.
It is also advisable to use a driekt (crossover)
connection, as switches also drop errornous packets.

Author: Szymon Piotrowski (sion111)
Posted on:

Rate this post
0 useful
not useful
Dose wrote:

> The starting code has a mistake in the preamble.

now it is 14x 0x5 then 0xD and 0x5 (as in 
https://en.wikipedia.org/wiki/Ethernet_frame)

As far as I understand Your code, it should be 13x 0x5, 0xD and than 
start of mac addressing?

Author: Verilog hotline (Guest)
Posted on:

Rate this post
0 useful
not useful
Szymon P. wrote:
> now it is 14x 0x5 then 0xD and 0x5 (as in
> https://en.wikipedia.org/wiki/Ethernet_frame)
>
> As far as I understand Your code, it should be 13x 0x5, 0xD and than
> start of mac addressing?

This is because of GMII is sending a byte at once and MII is sending two 
nibbles with least significant nibble first.

So

> now it is 14x 0x5 then 0xD and 0x5 (as in

should be okay.


Regarding the FCS, you could just send the frame with the 100 zero bytes 
from your PC (I already mentioned Ostinato which has a GUI and runs on 
Win/Linux but there are other command line tools also) and monitor it 
with wireshark, then compare the FCS that is automatically created with 
your FCS.
Also you can configure your PHY in loopback mode to PC side to know if 
your network card is in promiscuous mode.
For both you do not need to implement an RX in your FPGA.

Author: Lattice User (Guest)
Posted on:

Rate this post
1 useful
not useful
Szymon P. wrote:
> Dose wrote:
>
>> The starting code has a mistake in the preamble.
>
> now it is 14x 0x5 then 0xD and 0x5 (as in
> https://en.wikipedia.org/wiki/Ethernet_frame)
>

Which is wrong.

The IEEE 802.3 standards are part of the IEEE get program and available 
free of charge:

http://standards.ieee.org/about/get/802/802.3.html

MII is described in section 2,  chapter 22.
Table 22-3 shows exactly how to send the preamble.

Author: Szymon Piotrowski (sion111)
Posted on:

Rate this post
0 useful
not useful
> Table 22-3 shows exactly how to send the preamble.

You are right, thanks.

About checking FCS on wireshark or Ostinato, they just do not show any 
:/

Packets (raw ethernet frames, still without fcs shown) from Ostinato are 
captured as Malformed Packets with ARP protocol.

Author: Verilog hotline (Guest)
Posted on:

Rate this post
0 useful
not useful
Szymon P. wrote:
> Packets (raw ethernet frames, still without fcs shown) from Ostinato are
> captured as Malformed Packets with ARP protocol.

And are they returned when you enable PHY external loopback? Maybe you 
should also set a valid ether type, as otherwise this may be interpreted 
as length and may be discarded by your network card.

Author: Trundle Trollkönig (Guest)
Posted on:

Rate this post
1 useful
not useful
hi,

just google for Colasoft Packet Builder and download it. You can fill in 
your own Packet (bytewise) and it will calculate the CRC32 for you. I am 
using this programm to check the CRC32 values from my Ethernet packets, 
it works.

Author: Lattice User (Guest)
Posted on:

Rate this post
0 useful
not useful
In Wireshark have you set the promiscuous mode under capture options?

Author: Szymon Piotrowski (sion111)
Posted on:

Rate this post
0 useful
not useful
Ok, then, what about bit order. I assume that if my TX is 
(phytx3,phytx2,phytx1,phytx0) and i want to transmit 0x0806 I should do 
it like:
TX<=4'b1000;
TX<=4'b0000;
TX<=4'b0110;
TX<=4'b0000;

But what about FCS? The wiki states:
"the least-significant bit is transmitted first, except for the frame 
check sequence (FCS)."
For example, let the first byte of FCS be 0x14;
Should I do it the same way? (transmit 4, then 1), transmit it "as is" 
(1, then 4)...or reverse it from 0b00010100 to 0b00101000 and transmit 
it like 2 then 8, or 8 then 2?

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.