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Forum: FPGA, VHDL & Verilog VHDL (GHDL): can't have multiple entities in file?


Author: Edmund (Guest)
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Hello, this is my first post. I'm very new to digital logic and VHDL. I 
started by making some VHDL for just a clock, which I was able to 
compile with VHDL just fine, and simulate, and view the output in 
gtkwave.

What I was hoping to do next is just an 8-bit ripple adder. However, I'm 
stuck on an error. The following VHDL:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
    port (
        a, b: in std_logic;
        a_and_b: out std_logic
    );
end;

architecture behavior of and_gate is
begin
    process (a, b)
    begin
        a_and_b <= a and b;
    end process;
end;

entity xor_gate is
    port (
        a: in std_logic;
        b: in std_logic;
        a_xor_b: out std_logic
    );
end;

Fails with the errors:
$ ghdl -a 8_bit_adder.vhdl
8_bit_adder.vhdl:23:15: no declaration for "std_logic"
8_bit_adder.vhdl:24:15: no declaration for "std_logic"
8_bit_adder.vhdl:25:22: no declaration for "std_logic"
ghdl: compilation error

The error goes away if I delete the "xor_gate" entity. I'm surprised at 
the error as I don't know why I wouldn't be able to use the same type 
(std_logic) several times. Please help! :)

Author: Lothar Miller (lkmiller) (Moderator)
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Edmund wrote:
> library ieee;
> use ieee.std_logic_1164.all;
Thats missing before the second entity. Each VHDL module starts with the 
used libraries...

Author: Edmund (Guest)
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That was it!

Thank you.

Author: Edmund (Guest)
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Unfortunately, I've run into another error that I don't know how to 
interpret.

The following VHDL:
library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
    port (
        a: in std_logic;
        b: in std_logic;
        a_and_b: out std_logic
    );
end;

architecture behavior of and_gate is
begin
    process (a, b)
    begin
        a_and_b <= a and b;
    end process;
end;

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
    port (
        a: in std_logic;
        b: in std_logic;
        a_xor_b: out std_logic
    );
end;

architecture behavior of xor_gate is
begin
    process (a, b)
    begin
        a_xor_b <= a xor b;
    end process;
end;

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
    port (
        a: in std_logic;
        b: in std_logic;
        sum: out std_logic;
        carry: out std_logic
    );
end;

architecture structure of half_addr is
    component and_gate is
        port (
            a: in std_logic;
            b: in std_logic;
            a_and_b: out std_logic
        );
    end component;

    component xor_gate is
        port (
            a: in std_logic;
            b: in std_logic;
            a_xor_b: out std_logic
        );
    end component;
begin
    g1: xor_gate port map (
        a => a,
        b => b,
        a_xor_b => sum
    );
    g2: and_gate port map (
        a => a,
        b => b,
        a_and_b => carry
    );
end;
Yields:
$ ghdl -a 8_bit_adder.vhdl
8_bit_adder.vhdl:53:14: entity 'half_addr' was not analysed
ghdl: compilation error

It is probably obvious that this is my first structural VHDL 
architecture, I'm having trouble finding a good resource on VHDL 
syntax/semantics. Thank you in advance.

: Edited by Moderator
Author: Edmund (Guest)
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Oh uh.. nevermind. "half_addr" versus "half_adder".

Author: Lothar Miller (lkmiller) (Moderator)
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Edmund wrote:
> Oh uh.. nevermind
Ok, but in the next post with VHDL code try that (its to be found a few 
lines above the edit box):
Formatting options
[vhdl]VHDL code[/vhdl]

: Edited by Moderator

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