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Forum: FPGA, VHDL & Verilog how to add additional module to slow down the debounce


Author: me (Guest)
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i have 3 modules and have to add one more module to slow down my 
debounce problem by 360ns.

Author: Lothar Miller (lkmiller) (Moderator)
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me wrote:
> i have 3 modules
Very secret ones. Obviously.

> and have to add one more module to slow down my debounce problem
What is your "debounce problem"?
What is bouncing? And why?
What is your target (CPLD? ASIC? FPGA? Xilinx? Lattice? Altera?)
What toolchain and what HDL do you use?

Just a a very little hint: READ your own question as if you know NOTHING 
about your problem. Can you understand the question? No? Thats the way 
we see it also!

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