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Forum: FPGA, VHDL & Verilog VHDL, MSF 5 bit counter


Author: Edoardo Bernardi (edob95)
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Hello everyone,
I'm an italian student, so I apologize for my english, and I'm new in 
the forum, I have to do an exercise: the creation by MSF of a 5-bit 
counter using VHDL.
I have various input signals: a STOP signal which stops the count at the 
moment, a RESTART signal that resume the count, an UP_DOWN signal to 
choose the direction of the count and the signal of RESET.
I have alse 3 output signals: a signal END_C which indicates the end of 
the count, a signal START_C which indicates the start and a Q signal 
which indicates the value of the count.
This is my VHDL code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity esercizio3 is
port(CK, stop, restart, reset, up_down: in std_logic;
       end_c, start_c: out std_logic;
      Q: out std_logic_vector(4 downto 0));
end esercizio3;

architecture arc of esercizio3 is
    type stato is(ST0, ST1, ST2, ST3);
    signal ps, ns: stato;
    signal temp: std_logic_vector(4 downto 0);
    begin
      seq_proc: process(CK, RESET)
       begin
        if(RESET='0')then
        ps<=ST0;
        elsif(rising_edge(CK)) then
        ps<=ns;
        end if;
      end process seq_proc;

      comb_proc:process(RESTART, STOP, UP_DOWN, PS)
      begin
      end_c<='0';
      start_c<='0';
       case ps is
       when ST0=>
         temp<="00000";
         if(stop='0')then
         ns<=ST0;
         elsif(up_down='0')then
         ns<=ST1;
         else
         ns<=ST2;
         end if;

      when ST1=>
        temp<=temp-"00001";
        if(stop='0')then
        ns<=ST3;
        elsif(up_down='0')then
        ns<=ST1;
        else
        ns<=ST2;
        end if;

     when ST2=>
        temp<=temp+"00001";
        if(stop='0')then
        ns<=ST3;
        elsif(up_down<='0')then
        ns<=ST1;
        else
        ns<=ST2;
        end if;

     when ST3=>
        if(Restart='1')then
        ns<=ST3;
        elsif(up_down='0')then
        ns<=ST1;
        else
        ns<=ST2;
        end if;
        when others=>
        ns<=ST0;
     end case;
     Q<=temp;
     if(temp="00000")then
     start_c<='1';
     elsif(temp="11111")then
     end_c<='1';
     end if;
   end process comb_proc;
end arc; 

The compilation is successful but I get an error in model sim which is:

#**Error: (vsim-3601) Iteration limit reached at time 15ns.

I suppose there is a loop that does not allow proper execution.
Can you help me fix it? Thanks you.

Author: Lothar Miller (lkmiller) (Moderator)
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Edoardo Bernardi wrote:
> Can you help me fix it?
Your counter is inside a non-clocked process and forms therefore a 
combinatorial loop. Try to translate this: (its German) 
http://www.lothar-miller.de/s9y/archives/42-Kombin...

To keep things short: a counter must have a clock signal.

Author: Edoardo Bernardi (edob95)
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Ok so i have an infinite loop but how can I move the counter into a 
cloked process?? Can you please write me a couple of code strings, 
because this is the first time I realze a MSF using VHDL and I'm not 
practical with it??
Thanks you.

Author: Lothar Miller (lkmiller) (Moderator)
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One minor question in advance: what's MSF?

Edoardo Bernardi wrote:
> so i have an infinite loop
No. You have a combinatorial loop. That's something entirely 
different...

Author: Achim S. (Guest)
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Lothar Miller wrote:
> One minor question in advance: what's MSF?

I guess a "macchina a stati finiti" (known as FSM in other language ;-)

Author: Edoardo Bernardi (edob95)
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Yes I guess FSM but I wrote it in italian.
Anyway how can I solve my problem? I tried to move the counter into a
cloked process in different way but anything worked.

Author: Achim S. (Guest)
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Edoardo Bernardi wrote:
> I tried to move the counter into a
> cloked process in different way but anything worked.

What exactly is not working? How does your code look like now, and what 
error messages do you get?

Author: Lothar Miller (lkmiller) (Moderator)
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Achim S. wrote:
> What exactly is not working?
With the code above the counter forms a (gated) combinatorial loop.

Edoardo Bernardi wrote:
> Anyway how can I solve my problem?
If you wnat to use the 2 process style (1 clocked for the flipflops plus 
1 combinatorial), then you must implement a counter_present and a 
counter_next, as you did already for the FSM.
Keep in mind: even each counter is a finite state machine with defined.

First some hints:
1. Why do your states have such indifferent names like ST0, ST1, ST2, 
ST3?
Use SPEAKING names for your own data type.

2. And think about clever identation. It helps reading and understanding 
source code very much.

3. Do NOT use std_logic_vectors for calculations:
    signal temp: std_logic_vector(4 downto 0);
    :
        temp<=temp-"00001";
    :
        temp<=temp+"00001";
No one knows whether this calculation above is signed or unsigned...

4. "up_down" is a stupid name for a signal. Does it mean the counter 
counts UP and DOWN at the same time? Or what? Is '0' = UP or is '1' = 
UP?

5. "when others =>"
In your own type stato there is no other sate! All of the 4 states 
ST!..4 are explicitly decoded in the case. So: why "when others"?


But if I had to do that job with using of a FSM for the counter 
management, this could be my result:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity esercizio3 is
port(CK, stop, restart, reset, up_down: in std_logic;
     end_c, start_c: out std_logic;
     Q: out std_logic_vector(4 downto 0)
    );
end esercizio3;

architecture arc of esercizio3 is
  type stato is(IDLE, COUNT);
  signal state: stato;
  signal cnt: integer range 0 to 31;
begin
   seq_proc: process(CK)
   begin
      if rising_edge(CK) then

         case state is
            when IDLE =>
               if restart='1' then
                  state <= COUNT;
               end if;

            when COUNT =>
               if up_down='0' then  -- count UP
                  if cnt=31 then  cnt <= 0; -- overflow
                  else            cnt <= cnt+1;
                  end if;
               else                 -- count DOWN
                  if cnt=0 then  cnt <= 31; -- underflow
                  else           cnt <= cnt-1;
                  end if;
               end if;
               if stop='1' then
                  state <= IDLE;
               end if;
         end case;

         -- handle the reset as a synchronous signal
         if reset='1' then
            cnt <= 0;
            state <= IDLE;
         end if;
      end if;
   end process;

   -- some concurrent assignments
   Q <= std_logic_vector(to_unsigned(cnt,5));   
   start_c <= '1' when cnt=0  else '0';
   end_c   <= '1' when cnt=31 else '0';

end arc; 

: Edited by Moderator
Author: Achim S. (Guest)
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Lothar Miller wrote:
> With the code above the counter forms a (gated) combinatorial loop.

that's true, and in fact I had phrased my question wrongly. What I 
really wanted to know was how the actual code looks like and what 
error messages Edoardo gets, after he moved the counter to a clocked 
process.

Author: Lothar Miller (lkmiller) (Moderator)
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Achim S. wrote:
> how the actual code looks like and what error messages Edoardo gets,
> after he moved the counter to a clocked process.
Indeed, the latest code and its problems may be of interest here...  ;-)

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