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Forum: FPGA, VHDL & Verilog Help Beginner Make Stop watch


Author: John (Guest)
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Trying to make a stop watch that will stop when you hit the stop button 
that is what the while loop is for. I am an amateur and would really 
appreciate any help.

Thank You!

ERROR:HDLCompiler:806 - "/home/melvin/Desktop/Modern 
DIG/DashClock/DashClock.v" Line 85: Syntax error near "else".

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:20:50 04/10/2015 
// Design Name: 
// Module Name:    DashClock 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DashClock(
  input  START, STOP, CSS, RESET, clk,
  output a,b,c,d,e,f,g
    );
   reg [3:0] Enable;
   reg [15:0]TM;
   reg [18:0] Count ;
   wire Count_Max;
   
  always @(posedge clk)  //clk pulse at every 20ns
   begin
  
    if(Count == 500000)
       Count <= 0;
    else if (Count <= 500000)
       Count <= Count + 1;
   end
  
      assign Count_Max = ((Count == 500000)?1'b1:1'b0);
      
      
    
    reg Stop_Flg = 0;
  
    always @(posedge clk or posedge RESET)
    begin
    if(RESET)
      begin 
      TM [3:0] <= 0;
      TM [3:0] <= 0;
      TM [3:0] <= 0;
      TM [3:0] <= 0;
      end
        
    if (START == 1)  
      begin
      TM <= 0;
      
      
while (STOP !== Stop_Flg)
   begin

     if(Count_Max)
  begin  

   if(TM [3:0] == 4'b1001)
      begin

        TM [3:0] <= 4'b0000;
    if(TM [7:4] == 9)
                     begin
          TM [7:4] <= 4'b0000;

      if(TM [11:8] == 9)
          begin
            TM [11:8] <= 4'b0000;

        if(TM [15:12] == 9)
            begin
                Stop_Flg <= 1;
        else  // line 85 error                                                                                                                       
           TM [15:12] <= TM [15:12] +1;
                                end

         else 
                       TM [11:8] <= TM [11:8] +1;
               end

             else
        TM [7:4] <= TM [7:4] +1;
      end
                    
    else
      TM [3:0] <= TM [3:0] + 1;
    end// TM [3:0]
          
             end // If statement Count Max
         end // while
       end // IF Statement Start =1?
     end // always @ Clock
  
   reg [17:0] Mux_Count;
  reg [6:0]  Sev_Seg;
  reg        DP;
  
  always @ (posedge clk)
    begin
      Mux_Count <= Mux_Count +1;
    end
    
  always @ (*)
    begin
      case(Mux_Count[17:16])
       
       2'b00 :
        begin
        Sev_Seg <= TM[3:0];
        Enable <= 4'b0001;
        DP <= 0;
        end
        
       2'b01 :
        begin
        Sev_Seg <= TM[7:4];
        Enable <= 4'b0010;
        DP <= 1;
        end
        
       2'b10 :
        begin
        Sev_Seg <= TM[11:8];
        Enable = 4'b0100;
        DP <= 0;
        end
        
       2'b11 :
        begin
        Sev_Seg <= TM[15:12];
        Enable <= 4'b1000;
        DP <= 0;
        end
      endcase
     end
     
    reg [6:0] Convert;
    always @ (*)
      begin
       case(Sev_Seg)
        4'b0000 : Convert <= 7'b1111110;
        4'b0001 : Convert <= 7'b0110000;
        4'b0010 : Convert <= 7'b1101101;
        4'b0011 : Convert <= 7'b1111001;
        4'b0100 : Convert <= 7'b0110011;
        4'b0101 : Convert <= 7'b1011011;
        4'b0110 : Convert <= 7'b1011111;
        4'b0111 : Convert <= 7'b1110000;
        4'b1000 : Convert <= 7'b1111111;
        4'b1001 : Convert <= 7'b1111011;
        endcase
      end
    assign {a,b,c,d,e,f,g} = Convert;
    
    
endmodule

Author: Lattice User (Guest)
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John wrote:
>
> ERROR:HDLCompiler:806 - "/home/melvin/Desktop/Modern
> DIG/DashClock/DashClock.v" Line 85: Syntax error near "else".
>

This is caused by a nesting error. 2 lines before is an unclosed 
"begin".
Hard to spot, because of very bad indentation.

But there is a big rookie error, many beginners with programming (C, 
etc) background make: The while does not do what you expect!

Beginners should use while/for/... loops only in TEST benches, but never 
in anything which is targeted to hardware (i.e. FPGA).
Create a finite state machine instead.

(Your LED muxer is an example of a simple FSM)

Author: Lothar Miller (lkmiller) (Moderator)
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John wrote:
> Trying to make a stop watch
Try this original code there:
http://simplefpga.blogspot.de/2012/07/to-code-stop...

BTW: there's a design flaw in it making the clock inaccurate for 
1/5000000. "That's not that much!" you may say, but in fact its a very 
basic problem in a beginners design. The prescaler counts 5000001 steps 
instead only 5000000, one step too much... :-o

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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One more thing is this here:

if(RESET)
begin
  TM [3:0] <= 0;
  TM [3:0] <= 0;
  TM [3:0] <= 0;
  TM [3:0] <= 0;
end

Nice, isn't it? :-o

: Edited by Moderator

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