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Forum: FPGA, VHDL & Verilog Multi-source error


Author: Javier PA (lascameador)
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Hi guys!

I'm developing a system with an inout signal, like a bus.
I have two processes, driven by chip-enable signals, that they use this 
inout signal, but they never asssign it at the same time.

Any advices with multi source error?
Thanksss!

Author: Lothar Miller (lkmiller) (Moderator)
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Javier PA wrote:
> I have two processes, driven by chip-enable signals, that they use this
> inout signal,
That is a very, very ancient coding style...

Maybe the synthesizer cannot resolve the chip-enables in a way that this 
bus can be rolled out to the necessary MUX structure. Where do those 
chip-enables come from? Can you show the relevant code?

Author: Javier PA (lascameador)
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I'm going to try to explain that haha. If you don't understand anything 
tell me please because I'm spanish and it's hard to me write what i'm 
thinking exactly.

I'm developing an I2C slave, so I don't show my code because it's too 
big for my error I think. But i tried to do a scheme (attached file).

i'm working with an I2C bus. firstly process1 is an i2c slave, it gets 5 
bytes and ends transmision,  and then ,process2 works with user logic. 
they never work together (I use a state machine). Both proccesses have 
to read and write SDA line and here it is my mystake.

Author: Lattice User (Guest)
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For I2C use separate data out signals and combine them outside the 
processes.

Author: Lothar Miller (lkmiller) (Moderator)
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Javier PA wrote:
> But i tried to do a scheme (attached file).
You cannot do this inside a real FPGA. Only for simulation you can 
"connect" the signals in a testbench top level.
Apart from that technical possibility: it makes no sense to use an I2C 
bus inside an FPGA.

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