Forum: FPGA, VHDL & Verilog fpga vhdl serial read operation

Author: Kumar (Guest)
Posted on:

Rate this post
0 useful
not useful
I'm doing write and read operations from a SPI master.
While writing I'm simply writing the 14 bit address followed by 
read/write followed by 16 bit data. The slave then takes this info and 
does actual writing operation.

But while reading I'll first write to a register in the slave,  address 
followed by read/write bit (& no data or x"0000" because I'm reading). 
The very next cycle I want data to be avaialable for reading. But the 
slave takes sometime/cycles to go fetch the data from the address I just 
wrote to the register. While the slave goes and brings the data for me I 
want to keep my spi master idle and continue once the data is fetched, 
so I can read it serially at spi master using a miso line. How can I do 

(I'm using a simple shift register spi to shift and serially transmit 32 

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Kumar wrote:
> How can I do this.
Read your own post as if you know NOTHING about your system and your 
problem (thats the way all of us must do it). When you done that: can 
you understand the question?

Kumar wrote:
> a SPI master ... the slave
What is the "a master" and what is "the slave"?

> The very next cycle
What is the "very next cycle"? The "very next cycle" of what?

Kumar wrote:
> While the slave goes and brings the data for me I want to keep my spi
> master idle
You know that SPI is only 2 shift registers coupled behind each other 
(or in a loop). So if you want get something from the slave, the master 
must be active and generate the SLCK at least. The slave itself 
doesn't "go" anywhere...

Author: P. K. (pek)
Posted on:

Rate this post
0 useful
not useful
The environment variables of your question are pretty undefined, but as 
you write to an FPGA forum, I assume that your slave is located in an 

Furthermore undefined is the clock speed of your SPI. "Usually", it is 
quite slow compared to the FPGA system clock.

So I assume you implement your SPI by oversampling the inputs and 
trigger FPGA internal actions based on SPI clock edge detection.

So with all those assumptions, the solution is pretty easy: After the 
address have been applied, you read your register anyway, in parallel to 
the incoming read/write bit. If the bit turns out to indicate "read", 
you have your data already stored in the output shift register.

Because (as assumed earlier) the system clock is by far faster than the 
SPI clock, you have plenty of system cycles to do your register read 
during reception of the read/write bit.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.