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Forum: FPGA, VHDL & Verilog warning when synthesis


Author: afsoon (Guest)
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hello
please help!!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplexer is

port(a:in bit_vector(3 downto 0);
     z:out bit;
     s:in bit_vector(1 downto 0));

end multiplexer;

architecture Behavioral of multiplexer is
begin
z<= a(0) when s="00" else
    a(1) when s="01" else
    a(2) when s="10" else
    a(3);
end  Behavioral;

when program cpld xc9572 this warning is

warning: cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F =

and output dont show on board.

Author: Duke Scarring (Guest)
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afsoon wrote:
> warning: cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F =

The error is in .ucf file of your project.

Duke

Author: Lothar Miller (lkmiller) (Moderator)
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afsoon wrote:
> when program cpld xc9572 this warning is
Which part of which toolchain is warning?

> and output dont show on board.
On which board?

> AUTO_TS_F2F =
What does F2F mean? It means "Flipflop To Flipflop", and because you 
don't have any flipflops in your design this (automatically generated) 
constraint cannot be applied.

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