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Forum: FPGA, VHDL & Verilog Parallel MAC unit based on modified booth algorithm


Author: Jithin Smmb (Company: gstek) (vanisha)
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The below diagram is the parallel MAC structure.  In parallel MAC both 
partial product addition and accumulation take place at same time.
http://i.stack.imgur.com/aYJKo.jpg

The partial product summation + accumulation unit of above parallel mac 
is given below. http://i.imgur.com/Jd8WIyD.jpg

My problem : When I give input to multiplier as 00000101(5) and 
00001000(8) what will be the values 
produced(P0[7:0],P1[7:0],P2[7:0],P3[7:0] And S0,S1,S2,S3 And N0,N1,N2,N3 
that can be used as input of partial product generation + accumulation 
stage.

The complete document is shared below. 
http://www.mediafire.com/view/zoh8zuand88zkqx/05337888_2.pdf
Please share your ideas.I need to continue my project based on your 
replies.
Thanks.

Author: Duke Scarring (Guest)
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Jithin Smmb wrote:
> When I give input to multiplier as 00000101(5) and
> 00001000(8) what will be the values
> produced(P0[7:0],P1[7:0],P2[7:0],P3[7:0] And S0,S1,S2,S3 And N0,N1,N2,N3
> that can be used as input of partial product generation + accumulation
> stage.
Use a testbench and a simulator to spy out.

Duke

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