Forum: FPGA, VHDL & Verilog Xilinx 8.1 & Xilinx 14.7 Version will not compile my design

Author: Lewis Mbuthia (Company: Scientech Technologies) (loumbut5)
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I designed the processor DorQ which is attached. It compiles fine in 
Quartus 2 but my business partners use Xilinx 8.1 & Xilinx 14.7 Version 
and on these software, it shows errors which are also attached to this 
Could someone please provide a solution to this problem. Is there a 
setting we can change on Xilinx 8.1 & Xilinx 14.7 Version that will do 
away with the error messages.
Thanks for your reply.

Author: Duke Scarring (Guest)
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The message say, that there are two outputs are connected:
ac923: acff port map (wire1(2500 downto 2500), wire1(2501 downto 2501), wire0(2501 downto 2501), wire0(2500 downto 2500));
bc1579: bcff port map (wire0(2501 downto 2501), wire0(2502 downto 2502), wire1(2502 downto 2502), wire1(2501 downto 2501));

But your provided code is not human readable. Sorry, I can't help.

Did the error also occur, if you try to generate a bitfile?


Author: Lothar Miller (lkmiller) (Moderator)
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Lewis Mbuthia wrote:
> It compiles fine in Quartus 2
What target?

You use extensively inout ports inside a FPGA. But FPGAs don't have 
bidirectional ports in them anymore. Thes also don't have a 'Z' inside. 
So every bidirectional connection must be resolved at compile time to a 
unidirectional mux-solution. That looks fairly tricky in the supplied 

Lewis Mbuthia wrote:
> it shows errors which are also attached to this thread.
Errors messages in PNG format? Why not as raw text as they are 
displayed in your computer?

1.png: the syntax check just tells, that theres no semicolon or comma 
missing. Nearly useless...
2.png: "Synthesize failed" is NOT a error message, its just a final 
result. Absolutely useless...
3.png: A multi-source means just: you connected two outputs together. Or 
in more sophisticated words: you have more than one driver on this 

I don't see a solution for your problem. The design looks incredibly 
tricky. And it looks like it is not a design built for a FPGA.

: Edited by Moderator
Author: ElKo (Guest)
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WOW - That's what I call massive Crossposting. I thought, that the 
people nowadays know, not to crosspost?

Only the entry in edaboard I'm missing? [edit: found it, but as another 
question. See below.]

And what the hack is DorQ??? I can find only these interesting articles 
with naming such thing. Definitly worth the reading! Regarding to the 
crossposting and the mail-address, I asume that this is also from you, 
Lewis Mbuthia?

The code looks like a prank to me. But definitly not as a accelerating 
USB-Coprocessor. No explanation, what it is supposed to do. Whether it's 
complete. Nor the explanation of existing and running configurations... 
(I asume, there is no running configuration on a FPGA, and if there is, 
it isn't doing, what the descriptions says.)

But it's also funny, to look further. Only one example of the 
company-page scientechworld.com/careers.php : "At Scientech we have a 
vision of where we want to go, and it's really exciting. [...]" :-) 
Thanks for the funny workbreak!
Btw, it is often worth, to read the entries of embdev.net. ;-) (I'm 
impressed about your patiance, Lothar, to answer many of those 
questions! Good Job!)

 - ElKo


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