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Forum: FPGA, VHDL & Verilog 16 bit serial multiplier


Author: Omar (Guest)
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Hello

Im trying to write the behavioral code for a serial 16 bit multiplier. 
However, my output is always 0 for some reason. I used the debugging 
feature in vcs and apparently my R1,R2,R3 values are not being updated 
by the A values. Below are my source code and test bench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity SerialMultiplier1 is
port(A,B: IN std_logic_vector(15 downto 0);
     reset: IN std_logic;
     X: OUT std_logic_vector(31 downto 0));
end SerialMultiplier1;

architecture behavior of SerialMultiplier1 is
signal R1,R2,R3: std_logic_vector(31 downto 0) := (others => '0');

begin

process(reset)
begin 
  if reset='1' then
    X <= (others => '0');
  end if;
end process;

process(A,B)

begin
  for i in 0 to 31 loop
  
    if i = 0 then
      if B(i) = '1' then
        R1(15+i downto i) <= A(15 downto 0);
      else
        R1(15+i downto i) <= (others => '0');
      end if;
      X(i) <= R1(i);
    
    elsif (i>0 and i<16) then
      if B(i) = '1' then
        R2(15+i downto i) <= A(15 downto 0);
      else
        R2(15+i downto i) <= (others => '0');
      end if;
      R3 <= unsigned(R1) + unsigned(R2); X(i) <= R3(i);
      R1 <= R3; R2 <= (others => '0');
    
    else
      X(i) <= R3(i);
    end if;
  
  end loop;
end process;
end behavior;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity tb_SerialMultiplier1 is
end tb_SerialMultiplier1;

architecture behavior of tb_SerialMultiplier1 is
  component SerialMultiplier1
     port(A,B: IN std_logic_vector(15 downto 0);
          reset: IN std_logic;
          X: OUT std_logic_vector(31 downto 0));
  end component;

signal A,B: std_logic_vector(15 downto 0);
signal reset: std_logic;
signal X: std_logic_vector(31 downto 0);

begin
DUT: SerialMultiplier1 port map(A,B,reset,X);

process
begin
wait for 0 ns;
A<=x"0002";B<=x"0004";reset<='1';
wait for 10 ns;
reset<='0';
wait for 10 ns;
--A<=x"000B";B<=x"000A";
--wait for 10 ns;
--A<=x"0111";B<=x"0011";
--wait for 10 ns;
end process;
end behavior;    

Author: Lothar Miller (lkmiller) (Moderator)
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1. With that loop in VHDL you don't generate serial hardware. Instead 
you get a parallel multiplier.

2. You will not get this VHDL code on real hardware, because the signal 
X is driven from two sources.

A serial multiplier as I see it will need a clock, a shift register and 
an adder. Then with each clock the first operand is shifted one further 
and summed up, if the bit in the second operand is set. After 16 clock 
cycles the multiplication is done...

: Edited by Moderator
Author: Thomas Reinemann (Company: abaxor engineering) (abaxor)
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Lothar Miller wrote:
> A serial multiplier as I see it will need a clock, a shift register and
> an adder. Then with each clock the first operand is shifted one further
> and summed up, if the bit in the second operand is set. After 16 clock
> cycles the multiplication is done...

Is not. A 16 bits x 16 bits multiplication will lead to a 32 bits 
product which needs 32 clock. Furthermore 16 adders are needed.

See

http://www.abaxor.de/publications/diss/diss_reinemann.pdf

page 29.

It's in German.

Tom

Author: -gb- (Guest)
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> Furthermore 16 adders are needed.

Or 16 clock cycles if you use 1 only adder.

Author: -gb- (Guest)
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Author: Omar Rashad (Guest)
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Hi,

I have managed to write the behavioral code for it successfully. 
However, I am find it difficult to write the structural code for it 
because using for-generate statements to use the FA and HA components 
(that is required) means we cannot use a process. But if we don't use a 
process, how can we clock it?

Author: Lothar Miller (lkmiller) (Moderator)
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Omar Rashad wrote:
> I am find it difficult to write the structural code for it because using
> for-generate statements to use the FA and HA components (that is
> required) means we cannot use a process.
A multiplier usually does not need a clock at all. it can be implemented 
completly as a combinatorial description. So first you have to answer: 
do you need a clock at all?

> But if we don't use a process, how can we clock it?
This is a synthesizeable concurrent description of a clocked D-flipflop:
   FF_Dout <= FF_Din when rising_edge(clk);


BTW: doing VHDL with structural description is like drilling holes in 
steel with a wooden stick. Its just an old fashioned way to waste 
time...

And doing VHDL without using a process is like driving a car without a 
gearbox or only in the first gear: nearly senseless...

For any contemporary FPGA you write a multiplication this way:
   result <= a*b;

: Edited by Moderator

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