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Forum: FPGA, VHDL & Verilog State Machine with accumulator in VHDL


Author: Sony (Guest)
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Hello,
    I need a State Machine in VHDL, that receives a start, then "read" a 
8-bit value, then sums it with the accumulated values(initialy 0), then 
put the result in a register, and then do all of it again, since the 
scan of the 8-bit value, until the register with 16-bit is totally 
filled. Can someone help me with this?

Author: Sony (Guest)
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PS.: Each of these steps, after a clock signal.

Author: Bitflüsterer (Guest)
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Take your description and elaborate. It's not really far from the 
result.

Consider the following questions:

What is "a start"? A pulse? A level?

What is the disctinction between your "device" and an ordinary counter? 
If there is any? If there is indeed none (or only a slight one), try to 
implement a counter.

What does "... until the register with 16-bit is totally filled." 
acutally mean? From a theretical point of vier: How many 8-Bit unsigneed 
number (are they?) may you add before a 16-Bit unsigned overflows?

Author: Bitflüsterer (Guest)
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Oops. Some typos:

What does "... until the register with 16-bit is totally filled."
auctually mean? From a theoretical point of view: How many 8-Bit 
unsigneed
number (are they?) may you add before a 16-Bit unsigned overflows?

Author: Lothar Miller (lkmiller) (Moderator)
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Sony wrote:
> "read" a 8-bit value
From an 8 bit port?

Sony wrote:
> until the register with 16-bit is totally filled.
And then? Discard the value and wait for the next start signal?

Or let it say the other way: what is this for? Is it just homework, or 
is it a part of something else? If the second: what is it part of?

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