EmbDev.net

Forum: FPGA, VHDL & Verilog while loop running +64 how come?


Author: John Mayer (215)
Posted on:

Rate this post
0 useful
not useful
I have this codepiece
http://pastebin.com/nLyHXp8h
which is giving some problems..
I am getting a error message saying that it is getting looped more thank 
64 times, which i do not understand how that even is possible, since I 
increment the check value inside the loop each time.

I would be very glad if anyone could see where i am going wrong.

Author: John Mayer (215)
Posted on:

Rate this post
0 useful
not useful
could the problem be that my conditions isn't constant?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
John Mayer wrote:
> could the problem be that my conditions isn't constant?
No.
The problem ist, that you think VHDL is a programming language like C. 
Let me tell you: it isn't. It is far, far away from C or Basic or 
something like that!

Lets take this:
       while (pointer <= (3)) loop
               LED <= LISTEN(pointer);
               pointer := pointer + 1;
       end loop;
You will not be able to get this on hardware. It is just a 
"combinatorial loop". Do you want to know more? Try that with google 
translator:
http://www.lothar-miller.de/s9y/archives/42-Kombin...

The whole coding style is completely software based (variables, 
functions...) and this will lead to nowhere in VHDL. Did you do the 
blinking LED (= "Heollo Wolrd!" of hardware) and a chasing light before 
this code?

Pls attach your complete vhdl file here. then we can have a close look 
at it...

Author: John Mayer (215)
Posted on:

Rate this post
0 useful
not useful
complete code:
http://pastebin.com/Z4NxaeNd

I've replaced the while loop with an if statement.. which seem to work.
But for some reason i can when my pointer becomes larger than the size 
of my array, it just start pointing from the beginning, and continues??

How come?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
John Mayer wrote:
> complete code:
> http://pastebin.com/Z4NxaeNd
I will not read this that, because
Lothar Miller wrote:
> Pls attach your complete vhdl file here. then we can have a close look
> at it...
However...

> How come?
Your "problem" is well known and called "wrap around". Workaround: just 
don't try to access an index behind the last element.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.