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Forum: FPGA, VHDL & Verilog error with if generate


Author: bob (Guest)
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Hi all,

I got some errors when I try to compile the following code:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library peb_lib;
use peb_lib.all;

entity adc_simu is
     
  port(  CLK     : in  std_logic;
    MODE    : in real;
    OF_out  : out std_logic; -- OF pin
    D       : out std_logic_vector(13 downto 0)
      );
    
end adc_simu;

architecture archi of adc_simu is  

component adc

  generic (RefH, RefL: real;
     VDD: real);
     
  port(  Ain_pos : in real;
    Ain_neg : in  real;
    CLK     : in  std_logic;
    MODE    : in real;
    OF_out  : out std_logic; -- OF pin
    D       : out std_logic_vector(13 downto 0)
      );
    
end component;

component square_generator

  generic(LOW  : real;
    HIGH : real);
  
  port(wave: out real);
  
end component;

component triangle_generator

  generic(AMP: real;
    OFFSET: real;
    FREQ: real;
    PHASE :real);
  
  port(wave: out real);
  
end component;

component sinus_generator

  generic(AMP    : real;
    OFFSET : real;
    FREQ   : real;
    PHASE  : real);

  port(sinus: out real);
  
end component;

component sawtooth_generator

  generic(AMP: real;
    OFFSET: real;
    FREQ: real;
    PHASE : real);
  
  port(sawtooth: out real);

end component;

signal plus: real;
signal moins: real;

type waveform is (sinus, triangle, sawtooth, square);

signal wave_type: waveform := sinus;

begin

  TRI:if wave_type = triangle generate
              Vplus: triangle_generator 
                     generic map (AMP => 1.0,
                                  OFFSET => 1.5,
                                  FREQ => 100000.0,
                                  PHASE => 0.0)
                              
                     port map (plus);
          
               Vmoins: triangle_generator
                     generic map (AMP => 1.0,
                                  OFFSET => 1.5,
                                  FREQ => 100000.0,
                                  PHASE => 180.0)
          
                     port map (moins);

  end generate TRI;
      
  SQ:if wave_type = square generate
               Vplus: square_generator
                     generic map (LOW => 1.0,
                                  HIGH => 0.000122)    

                     port map (plus);
              
               Vmoins: square_generator
                      generic map (LOW => 0.000122,
                                   HIGH => 0.000244)
  
                     port map (moins);

  end generate SQ;

  SIN: if wave_type = sinus generate
                Vplus: sinus_generator
                      generic map (AMP => 1.0,
                                   OFFSET => 1.5,
                                   FREQ => 10000000.0,
                                   PHASE => 0.0)
             
                      port map (plus);
  
                Vmoins: sinus_generator
                      generic map (AMP => 1.0,
                                   OFFSET => 1.5,
                                   FREQ => 10000000.0,
                                   PHASE => 180.0)                  
                             
                       port map (moins);
  
  end generate SIN;
  
  SAW: if wave_type = sawtooth generate
                 Vplus: sawtooth_generator
                      generic map (AMP => 3.3,
                                   OFFSET => 1.65,
                                   FREQ => 10000000.0,
                                   PHASE => 0.0)
        
                      port map (plus);

                 Vmoins: sawtooth_generator
                      generic map (AMP => 3.3,
                                   OFFSET => 1.65,
                                   FREQ => 10000000.0,
                                   PHASE => 180.0)
             
                      port map (moins);
  
  end generate SAW;
       
  CAN: adc generic map (RefH => 1.0, RefL => -1.0, VDD => 3.3)
  
           port map (plus, moins, CLK, MODE, OF_out, D);
    
end archi;

Errors are:

../RTL/adc_simu.vhdl:
        TRI:            if wave_type = triangle generate
                                   |
ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,92|18): illegal reference of a 
signal (WAVE_TYPE) during static elaboration [12.3].
        SQ:             if wave_type = square generate
                                   |
ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,102|17): illegal reference of 
a signal (WAVE_TYPE) during static elaboration [12.3].
        SIN:            if wave_type = sinus generate
                                   |
ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,112|18): illegal reference of 
a signal (WAVE_TYPE) during static elaboration [12.3].
        SAW:            if wave_type = sawtooth generate
                                   |
ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,122|18): illegal reference of 
a signal (WAVE_TYPE) during static elaboration [12.3].

Can you tell me what is wrong in my code please!

Author: ChristophZ (Guest)
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bob wrote:
> type waveform is (sinus, triangle, sawtooth, square);
>
> signal wave_type: waveform := sinus;

For the condition in your "if...generate" construct you have to use a 
generic or a constant, because both are static values when you are doing 
a synthesis or the simulator compiles your sources.

bob wrote:
> ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,122|18): illegal reference of
> a signal (WAVE_TYPE) during static elaboration [12.3].

Read: "You are giving me a signal to decide what I should do, but a 
signal is some thing dynamic and I have to do a static (permanent) 
decision."

Author: bob (Guest)
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Thanks for your answer!

So, if I understand right I have to remplace the type waveform by a 
integer or generic type in the condition?

Author: ChristophZ (Guest)
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bob wrote:
> So, if I understand right I have to remplace the type waveform by a
> integer or generic type in the condition?

No. You don't have to replace the type. You can use any type and all the 
types you created yourself.

bob wrote:
> signal wave_type: waveform := sinus;

You have to chance wave_type, you can't use a signal here. You have to 
use a generic (defined in the entity) or in this case simply replace the 
word "signal" with "constant".

Author: Lothar Miller (lkmiller) (Moderator)
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bob wrote:
> So, if I understand right I have to remplace the type waveform by a
> integer or generic type in the condition?
You understood him wrong. I'm not sure if it works, but try this:
constant wave_type: waveform := sinus;

Or try a generic (but then you will have to define a package with your 
data type and include that in your entity)...

Author: bob (Guest)
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Yeah I was wrong. Lothar you're right, I have tested your idea before 
your post and is giving me no error.

Thank you both of you!

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