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Forum: FPGA, VHDL & Verilog GTP Transciever


Author: Alexander Lutovid (lutovid)
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Hi all.
I have a problem with clock correction(CC) in GTP 
Transciever(transmitting data between two FPGA's). I have two bytes 
interface without 8b/10b coding.
For example i always send X"5555" and set clock correction sequence as 1 
byte X"55" in wizard. But RXCLKCORCNT always "000".
But when i set "Don't care" on CC seq - CC work correctly!
I'v tried X"AA" CC sequence - it does not work too, so i have RX buffer 
underflow sometimes.
As I understand, I have wrongly specified CC sequence, but i can't 
understand where i have mistaken.

Author: Duke Scarring (Guest)
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Alexander Lutovid wrote:
> For example i always send X"5555" and set clock correction sequence as 1
> byte X"55" in wizard. But RXCLKCORCNT always "000".
> But when i set "Don't care" on CC seq - CC work correctly!
In simulation or in hardware?

Author: Alexander Lutovid (lutovid)
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Duke Scarring wrote:
> Alexander Lutovid wrote:
>> For example i always send X"5555" and set clock correction sequence as 1
>> byte X"55" in wizard. But RXCLKCORCNT always "000".
>> But when i set "Don't care" on CC seq - CC work correctly!
> In simulation or in hardware?

In hardware between 2 FPGA's.
In simulation i haven't detect this problem;
When i connect RX to TX(physically) on one board it also works
correctly.(Because it does not need CC)

: Edited by User
Author: Alexander Lutovid (lutovid)
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It works)
When i set RX_DECODE_SEQ_MATCH_0 False
But i have one question: If i use 16 bit interface how i can use 8 
bit(or 16) CC sequence( CLK_COR_SEQ_1_1_0 - 10 bit)? otherwise byte 
alignment will be lost(my block, using RXSLIDE)

: Edited by User

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