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Forum: FPGA, VHDL & Verilog VHDL Code works, need help with testbench and isim


Author: Tai Tai (john9686)
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Hi!

I'm working on this function. I need some help. Here is my code. It 
works sythesizes and implements the design. When I create a testbench 
using xilink I get the code attached. I add binary value "222" to 
switches in testbench. When I run isim I get the attached image. Whats 
wrong???


T = Min[Max(A,512),B]xC

CODE:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity functionT is
    port(
        clk: in std_logic;
        switches: in std_logic_vector(9 downto 0);
        output: out std_logic_vector(9 downto 0)
    );
end functionT;

architecture ARCH of functionT is
--signals
signal A: unsigned(9 downto 0):=("0110101001"); -- A=425
signal B: unsigned(9 downto 0);
signal sig512: unsigned(9 downto 0):=("1000000000"); --sign512=512
signal T: unsigned(9 downto 0);
signal x, y, z: unsigned(9 downto 0);

begin
    B <= unsigned(switches); --something like that
    x <= A when A>sig512 else sig512;
    y <= x when x<B else B;
    z <= y * 3;
    T <= z(7 downto 0) & "00";
    output <= std_logic_vector(T);
end ARCH;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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> testbench_code.txt
None of my VHDL files end up with ".txt"
Why does yours?

> signal A: unsigned(9 downto 0):=("0110101001"); -- A=425
Because signal A is not in a register, it cannot store the assigned 
default value. So one timestep after the first initialisation the signal 
A will become "UUUUUU...". This results in the reported metavalue. Try 
it this way:
> constant A: unsigned(9 downto 0):=("0110101001"); -- A=425

Author: Tai Tai (john9686)
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just copy pasted the testbench.vhd to notepad. here is orginal 
testbench.vhd.

constant A: unsigned(9 downto 0):=("0110101001"); -- A=425
does not work. Is the error coming from my testbench code?
In the image attached the clock is default 0

Author: Duke Scarring (Guest)
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Tai Tai wrote:
> does not work.
You provocate a type mismatch (std_logic_vector vs. unsigned).

With these changes it will work:
33c33
< --USE ieee.numeric_std.ALL;
---
> USE ieee.numeric_std.ALL;
53c53
<    signal switches : std_logic_vector(9 downto 0) :=("0011011110"); --A=222;
---
>    signal switches : unsigned(9 downto 0) := to_unsigned( 222, 10);
66c66
<           switches => switches,
---
>           switches => std_logic_vector( switches),

Duke

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