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Forum: FPGA, VHDL & Verilog FPGA Register Map


Author: Rudy Ba (rudyb)
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Hi,
In my few years of experience with FPGA, I have noticed that always when 
a micro-processor is connected to an FPGA there is a set of 
Status/Control Register defined.
And the more interaction between FPGA and MicroProcessor, the more 
Status/Control register is necessary to be defined.
One thing that I always noticed is that all the set of Registers that is 
allocated for FPGA is always designed using actual Flip-Flops.
However, I was curious, for the case that we have a long list of FPGA 
registers (e.g. in the order of 60 registers) why we never implement 
this as a Block-RAM in the FPGA ?!

I noticed no matter how big or small the number of FPGA register set is, 
it is always implemented using Flip-Flops as opposed to Block-RAMs !

Any reason why we don't use block RAMs for this purpose?


Wouldn't that make more sense to implement this as block-RAMs if the 
number of registers are of huge order, since the more registers we have, 
we gonna eat up more flip-flop resources?

Thanks,
--Rudy

Author: Achim S. (Guest)
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Rudy Ba wrote:
> However, I was curious, for the case that we have a long list of FPGA
> registers (e.g. in the order of 60 registers) why we never implement
> this as a Block-RAM in the FPGA ?!

Block RAM can store big amounts of data in a elegant way. But at one 
point in time it allows only access to a small fraction of the stored 
data (only one of the e.g. 60 registers).

So if you can ensure, that at any point in time you only need the 
information of one single register (and don't care about the 59 others), 
you could work with block RAM.

But the typical situation is, that all the logic in your FPGA works in 
parallel and at any point in time it needs access to several/all control 
registers in parallel. Block RAM can no provide that.

Author: Rudy Ba (rudyb)
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Hi,
Thanks for the reply. Your answer makes perfect sense.
However, is that the only reason?
Let's say, hypothetically speaking, if I can assure that FPGA can only 
access one register at a time, is it still a wise solution to use RAM 
instead of flip-flop?

From reliability perspective, is it true to say that flip-flops are more 
robust than RAMs? or this is not a true statement.

I know that your answer is the main reason why we use flip-flops rather 
than RAM.
However, from aerospace application perspective that robustness is the 
main criteria, is this true to say that Flip-Flops are less susceptible 
to single event upsets than Static-RAMs are?

Thanks,
--Rudy

Author: Ottmar (Guest)
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RAM's are made of FF. In the same technology often of the similar FF as 
used for sequential logic. Therefore the SEU performance is similar.

Dedicated radiation hardned devices uses typically SEU hardned FF for 
sequential logic (e.g. triplication inside the FF cell). But for RAM is 
typically a simple standard FF used. RAM's are then protected against 
SEU by EDAC codes.

Author: Fpga Kuechle (fpgakuechle)
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Rudy Ba wrote:
> Any reason why we don't use block RAMs for this purpose?

FF can be reset (i.e. for Soft reboot), BRAM don't.

Author: daniel__m (Guest)
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Hi,

the decision if bram or ff (or in my case mixed) depends on the design. 
as already told, control-lines are often needed in parallel for example 
to active/deactive some blocks and therefore brams can't do that. but if 
a module needs only one set of parameter at a time (like a LUT) you can 
use brams. for example we use true dual port rams (brams) for a 
transformation of a video-stream.

Author: Rudy Ba (rudyb)
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Thanks a lot for all the explanations. They all make sense.

--Rudy

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