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Forum: FPGA, VHDL & Verilog Error (12007): Top-level design entity "components" is undefined


Author: SV VS (gaij1n)
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LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
  -- 2-to-1 multiplexer
  COMPONENT mux2to1 
    PORT (  w0, w1   : IN   STD_LOGIC ;
        s     : IN   STD_LOGIC ;
        f     : OUT   STD_LOGIC ) ;
  END COMPONENT ;
  -- D flip-flop with 2-to-1 multiplexer connected to D
  COMPONENT muxdff
    PORT (  D0, D1, Sel, Clock   : IN   STD_LOGIC ;
        Q       : OUT   STD_LOGIC ) ;
  END COMPONENT ;
  -- n-bit register with enable
  COMPONENT regne  
    GENERIC ( N : INTEGER := 4 ) ;
    PORT (  R     : IN   STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
        Resetn   : IN   STD_LOGIC ;
        E, Clock   : IN   STD_LOGIC ;
        Q     : OUT   STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
  END COMPONENT ;
-- n-bit right-to-left shift register with parallel load and enable
  COMPONENT shiftlne  
    GENERIC ( N : INTEGER := 4 ) ;
    PORT (  R     : IN     STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
        L, E, w  : IN     STD_LOGIC ;
        Clock  : IN     STD_LOGIC ;
        Q     : BUFFER   STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
  END COMPONENT ;

  -- n-bit left-to-right shift register with parallel load and enable
  COMPONENT shiftrne  
    GENERIC ( N : INTEGER := 4 ) ;
    PORT (  R     : IN     STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
        L, E, w  : IN     STD_LOGIC ;
        Clock  : IN     STD_LOGIC ;
        Q     : BUFFER   STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
  END COMPONENT ;
-- up-counter that counts from 0 to modulus-1
  COMPONENT upcount  
    GENERIC  ( modulus : INTEGER := 8 ) ;
    PORT  (   Resetn     : IN     STD_LOGIC ;
          Clock, E, L  : IN     STD_LOGIC ;
          R       : IN     INTEGER RANGE 0 TO modulus-1 ;
          Q       : BUFFER   INTEGER RANGE 0 TO modulus-1 ) ;
  END COMPONENT ;

  -- down-counter that counts from modulus-1 down to 0
  COMPONENT downcnt 
    GENERIC  ( modulus : INTEGER := 8 ) ;
    PORT (  Clock, E, L  : IN       STD_LOGIC ;
        Q       : BUFFER   INTEGER RANGE 0 TO modulus-1 ) ;
  END COMPONENT ;

END components ;

I just recently started to learn vhdl and I found this code online as I 
was  researching on how to use components. When I try to run it, I get 
that error.
Error (12007): Top-level design entity "components" is undefined
how do i fix it
I have attached the source file too its on page 8, thanks for your help 
in advance

Author: Murali BN (nmb)
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What he is basically telling you is to create package out of modules. To 
use a component you need not necessarily use a package. Just create a 
module, for example, and call that in your other modules where you want 
to use it (of course it should be added in your project).

See this for example: 
http://www.cs.fredonia.edu/zubairi/training/vhdlcompo.html

and this: 
http://www.doulos.com/knowhow/vhdl_designers_guide...

Author: SV VS (gaij1n)
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Thank you very much, I eventually figured out how to do it with the help 
of the second link. I came across it as I was trying to figure it out. 
This helps boost my confidence in my capabilities with VHDL, 1 step at a 
time, thanks again

Author: Lothar Miller (lkmiller) (Moderator)
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Murali BN wrote:
> Just create a module, for example, and call that in your other modules
> where you want to use it (of course it should be added in your project).
VHDL is no programming language where you "call" a component!!!
VHDL is a hardware description language. Here you must have a "picture" 
of a hardware inside your brain or on a sheet of paper (also called 
schematic), and this picture can afterwards be described with VHDL. If 
you cannot imagine what you are describing at the moment of typing, your 
VHDL code will result in problems...

Author: Murali BN (nmb)
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I am very sorry that I have used the word "call". The right word should 
have been Instantiation. Thank you for noting it to me.

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