EmbDev.net

Forum: FPGA, VHDL & Verilog Controlling a linear CCD with FPGA


Author: Murat GUNES (Company: BEAM Ar-Ge) (mguneskou)
Posted on:

Rate this post
0 useful
not useful
Hello everyone!

I am trying to make my own CCD controler board. For this aim I picked 
Toshiba TCD1304 CCD detector, Terasic DE0 Nano board with Altera Cyclone 
IV and FT2232H Mini Module from FTDI. The basic operation flow should be 
like this:

1- Generate the three clock signals which are required by CCD (I have 
done this)

2- Use the onboard ADC of DE0 Nano for to convert the data which comes 
from the CCD (I have some problems in that point. I can use the ADC but 
I am not sure about the data that comes from the CCD)

3- Write these data to the onboard SD Ram of DE0 Nano(Not yet)

4- Send these data to the computer using the FT2232H Mini Module(I have 
experience about this).

At step two; I have no idea about the output signal of the CCD. I read 
the manual of the CCD sensor and I couldn't undrstand how should I read 
the data from it. Here is the link for the datasheet of the CCD:

http://www.eureca.de/datasheets/01.xx.xxxx/01.04.x...

If I can learn how the CCD gives me the data then I will be able to read 
and write it to the board's RAM. And after that I already know how to 
use the FT2232H Mini Module with DE0 Nano.

I use Quartus II and Verilog by the way.

Any suggestion, link or example would be greatly appriciated.

Thanks...

Author: Karl Könner (Guest)
Posted on:

Rate this post
0 useful
not useful
Page 7 shows the output of the CCD:
For every shift cycle you get another signal at the output, which 
relates the number of charges of the photo-cell. the leading and the 
trailing charge-signal (marked as dummy) come from dummy cells, ie. do 
not corrospond to a pixel, so you may ignore them. (well, sometimes this 
pixel are used the generate a "black pixel reference level" but you will 
need a specialized ADC to benefit from this).


 Shortly after shifting-out a single element you shall smaple it from 
you ADC. So you can delaying the shift clock to generate the sample 
clock.

One option could be to operate with an higher clock in fpga say 300 MHz 
when the shift (pixel) clock is 50 MHz. then you have a counters runing 
at 300 MHz, if the counter is counts 0,1,2 shift clock is high, and if 
it counts 1,2,3 sample clock is High.  optimising the phase und pulse 
width of ccd shift gain and sample clock reduce the pixel noise a lot.


OK this is just a sketch, often a look into a datasheet of  a line-ccd
controller (Keyword :"Linear CCD  Driver" ) or of a linear ccd optimised 
ADC
i.e. 
http://www.analog.com/static/imported-files/data_s...).

Best regards,

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Karl Könner wrote:
> shift (pixel) clock is 50 MHz.
That fast? Slow down a little bit: the maximum master clock is 4MHz. And 
SH ist not the "shift clock", because there is no shift clock at all. 
With the SH pin you only control the shutter "opening"...

The process is to "clear" the ccd cells with a pulse on the ICG pin. 
Then with each forth master clock cycle new analog data is output on OS 
(so data rate is 1/4 the master clock).

Author: Karl Könner (Guest)
Posted on:

Rate this post
0 useful
not useful
Lothar Miller wrote:
> Karl Könner wrote:

> SH ist not the "shift clock", because there is no shift clock at all.
> With the SH pin you only control the shutter "opening"...


page 2, table "pin names", line "SH"  -> reads "Shift gate"


Anyway, every charged coupled device needs a shift signal (sometetime 
(internally, see block "Logic circuitry) generated by (internally) 
overlapping clock signals) to move (shift) the charges over the "bucket 
brigade". Shifting ist "essential" for CCD's, there is no CCD working 
without a "shift-circuitry/clock). (See 
http://en.wikipedia.org/wiki/Charge-coupled_device, search for the term 
"shift" (Ctrl-f))

After "forcing and finishing" this shift by controlling the signals to 
the CD-line,  you have to initiate the sampling of the analog output.


>The process is to "clear" the ccd cells with a pulse on the ICG pin.
>Then with each forth master clock cycle new analog data is output on OS
>(so data rate is 1/4 the master clock).
ACK

It's a bit confusing that there are 2 timing charts (p6/p7). At page 7 
it seems that after every SH-Pulse new data is presented at the signal 
output, where at page 6 there is just a single SH-Pulse.

I am more familiar with image sensor than with liniear sensors

Best regards,

Author: Murat GUNES (Company: BEAM Ar-Ge) (mguneskou)
Posted on:

Rate this post
0 useful
not useful
Thanx you both for your urgent replies. I will check the things you 
wrote.

Regards...

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.