Hi, all I am doing a traffic light controller project with using DE2 board... the code I have is compiled perfectly, but when I use the DE2 board, it doesn't work properly... Some lights should be turned on when I switch on.. but for some reason it keeps having the same issues although I try on and on. So I asked the professor about the issue, and he said this is logic problem... I hope you help me out. I attached the file of the code in case.
SJ Oh wrote: > the code I have is compiled perfectly I can write don some lines of VHDL tha compile rperfectly well, but the will do nonsens on the hardware. The debugger for VHDL is the funtional simulator. > but for some reason it keeps having the same issues Which ones? One question: How fast is your clock?
1 | elsif CLK'event and CLK = '1' then -- how fast .... |
2 | case traffic_light_controller is |
3 | when GR => |
4 | if count < sec_5 then |
5 | traffic_light_controller <= GR; |
6 | count <= Count+1; -- ... will count count up? |
7 | else
|
8 | traffic_light_controller <= YR; |
9 | count<=X"0"; --count is reset to zero |
10 | end if; |
Is it really 1Hz? This is not the problem, but for me it is a major mistake:
1 | type traffic_light_controller_type is (GR, RY, RR2, YR, RG, RR1); |
2 | signal traffic_light_controller: traffic_light_controller_type; |
3 | |
4 | |
5 | traffic_light_controller_machine: process (CLK,CLR) |
6 | begin
|
7 | if CLR='1' then |
8 | traffic_light_controller <= GR; |
9 | elsif CLK'event and CLK = '1' then |
10 | case traffic_light_controller is |
11 | when GR => |
12 | |
13 | when YR => |
14 | |
15 | when RR1 => |
16 | |
17 | when RG => |
18 | |
19 | when RY => |
20 | |
21 | when RR2 => |
22 | |
23 | when others => -- there are no remaining other states !!!!!! |
24 | |
25 | end case; |
when others is not necessary when all of the possible states are used. The signal traffic_light_controller has only 6 states and each of them is explicitly used, so there are no "others" remaining!
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