Hi! simple question can I use this kind of syntax into verilog :
1 | case(Fetched[24:4]) |
2 | 21'bzzzzzzzzzzzzzzzzzzzz0 :nextstate <= ADD; |
3 | 21'bzzzzzzzzzzzzzzzzz0zz1 :nextstate <= ADD; |
4 | 21'b000zzzzzzzzzzzzzz1001 :nextstate <= MUL; //mult |
5 | 21'b01zzzzzzzzzzzzzzz1001 :nextstate <= MUL; |
6 | 21'b10z00zzzzzzzz00001001 :nextstate <= MUL; |
7 | 21'b10z00zzzzzzzz00001001 :nextstate <= SDS; |
8 | 21'b100101111111111110001 :nextstate <= BAE; |
9 | default: nextstate <= UNKNOW; //should not happens |
10 | endcase
|
I have no error while simulating but have strange result (I'm student working on sim vision) thanks all :)