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Forum: FPGA, VHDL & Verilog Verilog Case : don't care


Author: Jag (Guest)
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Hi!
simple question
can I use this kind of syntax into verilog :
 case(Fetched[24:4])
                21'bzzzzzzzzzzzzzzzzzzzz0 :nextstate <= ADD;
                21'bzzzzzzzzzzzzzzzzz0zz1 :nextstate <= ADD;
                21'b000zzzzzzzzzzzzzz1001 :nextstate <= MUL; //mult
                21'b01zzzzzzzzzzzzzzz1001 :nextstate <= MUL;
                21'b10z00zzzzzzzz00001001 :nextstate <= MUL;
                21'b10z00zzzzzzzz00001001 :nextstate <= SDS;
                21'b100101111111111110001 :nextstate <= BAE;
                  default: nextstate <= UNKNOW; //should not happens
              endcase

I have no error while simulating but have strange result
(I'm student working on sim vision)

thanks all :)

Author: Jag (Guest)
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Author: Lattice User (Guest)
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Two mistakes:

1. 'z' is not don't care.  Use 'x'
2. Use "casex" instead of "case"

Author: Jag (Guest)
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thanx
I'll do that, but why casez is not ok here ?

Author: Lattice User (Guest)
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'z' ist not don't care, it stands for high impedance, a clearly defined 
state, at least for the simulator.

Author: Marcus Harnisch (mharnisch)
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Lattice User wrote:
> 'z' ist not don't care, it stands for high impedance, a clearly defined
> state, at least for the simulator.

It is actually casez that is preferable here. Specifically for this 
reason Verilog defines '?' as synonym for 'z'. With casex you wouldn't 
be able to distinguish unknowns and dont-cares since both use the same 
symbol.

Kind regards
Marcus

Author: Lattice User (Guest)
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Marcus Harnisch wrote:
> It is actually casez that is preferable here. Specifically for this
> reason Verilog defines '?' as synonym for 'z'. With casex you wouldn't
> be able to distinguish unknowns and dont-cares since both use the same
> symbol.

You are right, see IEEE Std 1364-2001 Chapter 9.5.1
To make the intent more vissible i suggest using casez with '?'.

(Sometimes i have to ask what standard writer are smoking)

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